Texas Instruments CC2650DK Benutzerhandbuch
Functional Description
12.3.4.1 Single Request
When a single request is detected (not a burst request), the
μDMA controller transfers one item and then
stops to wait for another request.
NOTE:
Channels 8, 13, 14, and 15 do not respond to a single request because waitonreq is tied low.
12.3.4.2 Burst Request
When a burst request is detected, the
μDMA controller transfers the number of items that is the lesser of
the arbitration size or the number of items remaining in the transfer. Therefore, the arbitration size should
be the same as the number of data items that the peripheral can accommodate when making a burst
request. For example, the UART/SPI, which use a mix of single or burst requests, could generate a burst
request based on the FIFO trigger level. In this case, the arbitration size should be set to the amount of
data that the FIFO can transfer when the trigger level is reached. A burst transfer runs to completion once
it starts and cannot be interrupted, even by a higher-priority channel. Burst transfers complete in a shorter
time than the same number of nonburst transfers.
be the same as the number of data items that the peripheral can accommodate when making a burst
request. For example, the UART/SPI, which use a mix of single or burst requests, could generate a burst
request based on the FIFO trigger level. In this case, the arbitration size should be set to the amount of
data that the FIFO can transfer when the trigger level is reached. A burst transfer runs to completion once
it starts and cannot be interrupted, even by a higher-priority channel. Burst transfers complete in a shorter
time than the same number of nonburst transfers.
It may be desirable to use only burst transfers and not allow single transfers (for example, when the
nature of the data is such that it only makes sense when transferred together as a single unit rather than
one piece at a time). The single request can be disabled in the [UDMA_SETBURST] register. By setting
the bit for a channel in this register, the
nature of the data is such that it only makes sense when transferred together as a single unit rather than
one piece at a time). The single request can be disabled in the [UDMA_SETBURST] register. By setting
the bit for a channel in this register, the
μDMA controller responds only to burst requests for that channel.
12.3.5 Channel Configuration
The
μDMA controller uses an area of system memory to store a set of channel control structures in a
table. The control table may have one or two entries for each
μDMA channel. Each entry in the table
structure contains source and destination pointers, transfer size, and transfer mode. The control table can
be located anywhere in system memory, but it must be contiguous and aligned on a 1024-byte boundary.
be located anywhere in system memory, but it must be contiguous and aligned on a 1024-byte boundary.
describes the memory layout of the channel control table. Each channel may have one or two
control structures in the control table: a primary control structure and an optional, alternate control
structure. The table is organized with all of the primary entries in the first half of the table, and with all the
alternate structures in the second half of the table. The primary entry is used for simple transfer modes
where transfers can be reconfigured and restarted after each transfer completes. In this case, the
alternate control structures are not used and therefore, only the first half of the table must be allocated in
memory; the second half of the control table is not necessary, and that memory can be used for
something else. If a more complex transfer mode is used, such as ping-pong or scatter-gather, then the
alternate control structure is also used and memory space should be allocated for the entire table.
structure. The table is organized with all of the primary entries in the first half of the table, and with all the
alternate structures in the second half of the table. The primary entry is used for simple transfer modes
where transfers can be reconfigured and restarted after each transfer completes. In this case, the
alternate control structures are not used and therefore, only the first half of the table must be allocated in
memory; the second half of the control table is not necessary, and that memory can be used for
something else. If a more complex transfer mode is used, such as ping-pong or scatter-gather, then the
alternate control structure is also used and memory space should be allocated for the entire table.
Any unused memory in the control table may be used by the application, which includes the control
structures for any channels that are unused by the application, as well as the unused control word for
each channel.
structures for any channels that are unused by the application, as well as the unused control word for
each channel.
Table 12-3. Control Structure Memory Map
Offset
Channel
0x0
0, Primary
0x10
1, Primary
...
...
0x1F0
31, Primary
0x200
0, Alternate
0x210
1, Alternate
...
...
0x3F0
31, Alternate
1040
Micro Direct Memory Access (µDMA)
SWCU117A – February 2015 – Revised March 2015
Copyright © 2015, Texas Instruments Incorporated