BenutzerhandbuchInhaltsverzeichnisTable of Contents2Revision History10Preface111 Architectural Overview131.1 Target Applications141.2 Overview141.3 Functional Overview171.3.1 ARM Cortex-M3171.3.1.1 Processor Core171.3.1.2 System Timer (SysTick)181.3.1.3 Nested Vector Interrupt Controller181.3.1.4 System Control Block181.3.2 On-Chip Memory181.3.2.1 SRAM181.3.2.2 Flash Memory191.3.2.3 ROM191.3.3 Radio191.3.4 AES Engine With 128-Bit Key Support191.3.5 General-Purpose Timers201.3.5.1 Watchdog Timer201.3.5.2 Always-on Domain201.3.6 Direct Memory Access201.3.7 System Control and Clock211.3.8 Serial Communications Peripherals211.3.8.1 UART221.3.8.2 I2C221.3.8.3 I2S231.3.8.4 SSI231.3.9 Programmable IOs241.3.10 Sensor Controller241.3.11 Random Number Generator251.3.12 cJTAG and JTAG251.3.13 Power Supply System251.3.13.1 Supply System251.3.13.1.1 VDDS261.3.13.1.2 VDDR261.3.13.1.3 Digital Core Supply271.3.13.1.4 Other Internal Supplies271.3.13.2 DC-DC Converter271.3.13.3 External Regulator Mode (1.65-V to 1.95-V Supply Voltage)272 The Cortex-M3 Processor282.1 The Cortex-M3 Processor Introduction292.2 Block Diagram292.3 Overview302.3.1 System-Level Interface302.3.2 Integrated Configurable Debug302.3.3 Trace Port Interface Unit312.3.4 Cortex-M3 System Component Details312.4 Programming Model312.4.1 Processor Mode and Privilege Levels for Software Execution322.4.2 Stacks322.4.3 Exceptions and Interrupts322.4.4 Data Types322.5 Coretex-M3 Core Registers332.5.1 Core Register Map342.5.2 Core Register Descriptions342.5.2.1 Cortex General-Purpose Register 0 (R0)342.5.2.2 Cortex General-Purpose Register 1 (R1)352.5.2.3 Cortex General-Purpose Register 2 (R2)352.5.2.4 Cortex General-Purpose Register 3 (R3)352.5.2.5 Cortex General-Purpose Register 4 (R4)362.5.2.6 Cortex General-Purpose Register 5 (R5)362.5.2.7 Cortex General-Purpose Register 6 (R6)362.5.2.8 Cortex General-Purpose Register 7 (R7)372.5.2.9 Cortex General-Purpose Register 8 (R8)372.5.2.10 Cortex General-Purpose Register 9 (R9)372.5.2.11 Cortex General-Purpose Register 10 (R10)382.5.2.12 Cortex General-Purpose Register 11 (R11)382.5.2.13 Cortex General-Purpose Register 12 (R12)382.5.2.14 Stack Pointer (SP)392.5.2.15 Link Register (LR)392.5.2.16 Program Counter (PC)402.5.2.17 Program Status Register (PSR)402.5.2.18 Priority Mask Register (PRIMASK)442.5.2.19 Fault Mask Register (FAULTMASK)452.5.2.20 Base Priority Mask Register (BASEPRI)462.5.2.21 Control Register (CONTROL)472.6 Instruction Set Summary472.7 Cortex-M3 Processor Registers502.7.1 CPU_ITM Registers512.7.1.1 STIM0 Register (Offset = 0h) [reset = 0h]522.7.1.2 STIM1 Register (Offset = 4h) [reset = 0h]532.7.1.3 STIM2 Register (Offset = 8h) [reset = 0h]542.7.1.4 STIM3 Register (Offset = Ch) [reset = 0h]552.7.1.5 STIM4 Register (Offset = 10h) [reset = 0h]562.7.1.6 STIM5 Register (Offset = 14h) [reset = 0h]572.7.1.7 STIM6 Register (Offset = 18h) [reset = 0h]582.7.1.8 STIM7 Register (Offset = 1Ch) [reset = 0h]592.7.1.9 STIM8 Register (Offset = 20h) [reset = 0h]602.7.1.10 STIM9 Register (Offset = 24h) [reset = 0h]612.7.1.11 STIM10 Register (Offset = 28h) [reset = 0h]622.7.1.12 STIM11 Register (Offset = 2Ch) [reset = 0h]632.7.1.13 STIM12 Register (Offset = 30h) [reset = 0h]642.7.1.14 STIM13 Register (Offset = 34h) [reset = 0h]652.7.1.15 STIM14 Register (Offset = 38h) [reset = 0h]662.7.1.16 STIM15 Register (Offset = 3Ch) [reset = 0h]672.7.1.17 STIM16 Register (Offset = 40h) [reset = 0h]682.7.1.18 STIM17 Register (Offset = 44h) [reset = 0h]692.7.1.19 STIM18 Register (Offset = 48h) [reset = 0h]702.7.1.20 STIM19 Register (Offset = 4Ch) [reset = 0h]712.7.1.21 STIM20 Register (Offset = 50h) [reset = 0h]722.7.1.22 STIM21 Register (Offset = 54h) [reset = 0h]732.7.1.23 STIM22 Register (Offset = 58h) [reset = 0h]742.7.1.24 STIM23 Register (Offset = 5Ch) [reset = 0h]752.7.1.25 STIM24 Register (Offset = 60h) [reset = 0h]762.7.1.26 STIM25 Register (Offset = 64h) [reset = 0h]772.7.1.27 STIM26 Register (Offset = 68h) [reset = 0h]782.7.1.28 STIM27 Register (Offset = 6Ch) [reset = 0h]792.7.1.29 STIM28 Register (Offset = 70h) [reset = 0h]802.7.1.30 STIM29 Register (Offset = 74h) [reset = 0h]812.7.1.31 STIM30 Register (Offset = 78h) [reset = 0h]822.7.1.32 STIM31 Register (Offset = 7Ch) [reset = 0h]832.7.1.33 TER Register (Offset = E00h) [reset = X]842.7.1.34 TPR Register (Offset = E40h) [reset = X]862.7.1.35 TCR Register (Offset = E80h) [reset = X]872.7.1.36 LAR Register (Offset = FB0h) [reset = X]892.7.1.37 LSR Register (Offset = FB4h) [reset = X]902.7.2 CPU_DWT Registers922.7.2.1 CTRL Register (Offset = 0h) [reset = X]932.7.2.2 CYCCNT Register (Offset = 4h) [reset = X]952.7.2.3 CPICNT Register (Offset = 8h) [reset = X]962.7.2.4 EXCCNT Register (Offset = Ch) [reset = X]972.7.2.5 SLEEPCNT Register (Offset = 10h) [reset = X]982.7.2.6 LSUCNT Register (Offset = 14h) [reset = X]992.7.2.7 FOLDCNT Register (Offset = 18h) [reset = X]1002.7.2.8 PCSR Register (Offset = 1Ch) [reset = 0h]1012.7.2.9 COMP0 Register (Offset = 20h) [reset = 0h]1022.7.2.10 MASK0 Register (Offset = 24h) [reset = X]1032.7.2.11 FUNCTION0 Register (Offset = 28h) [reset = X]1042.7.2.12 COMP1 Register (Offset = 30h) [reset = 0h]1062.7.2.13 MASK1 Register (Offset = 34h) [reset = X]1072.7.2.14 FUNCTION1 Register (Offset = 38h) [reset = X]1082.7.2.15 COMP2 Register (Offset = 40h) [reset = 0h]1102.7.2.16 MASK2 Register (Offset = 44h) [reset = X]1112.7.2.17 FUNCTION2 Register (Offset = 48h) [reset = X]1122.7.2.18 COMP3 Register (Offset = 50h) [reset = 0h]1132.7.2.19 MASK3 Register (Offset = 54h) [reset = X]1142.7.2.20 FUNCTION3 Register (Offset = 58h) [reset = X]1152.7.3 CPU_FPB Registers1172.7.3.1 CTRL Register (Offset = 0h) [reset = X]1182.7.3.2 REMAP Register (Offset = 4h) [reset = X]1192.7.3.3 COMP0 Register (Offset = 8h) [reset = X]1202.7.3.4 COMP1 Register (Offset = Ch) [reset = X]1212.7.3.5 COMP2 Register (Offset = 10h) [reset = X]1222.7.3.6 COMP3 Register (Offset = 14h) [reset = X]1232.7.3.7 COMP4 Register (Offset = 18h) [reset = X]1242.7.3.8 COMP5 Register (Offset = 1Ch) [reset = X]1252.7.3.9 COMP6 Register (Offset = 20h) [reset = X]1262.7.3.10 COMP7 Register (Offset = 24h) [reset = X]1272.7.4 CPU_SCS Registers1292.7.4.1 ICTR Register (Offset = 4h) [reset = X]1312.7.4.2 ACTLR Register (Offset = 8h) [reset = X]1322.7.4.3 STCSR Register (Offset = 10h) [reset = X]1332.7.4.4 STRVR Register (Offset = 14h) [reset = X]1342.7.4.5 STCVR Register (Offset = 18h) [reset = X]1352.7.4.6 STCR Register (Offset = 1Ch) [reset = X]1362.7.4.7 NVIC_ISER0 Register (Offset = 100h) [reset = X]1372.7.4.8 NVIC_ISER1 Register (Offset = 104h) [reset = X]1402.7.4.9 NVIC_ICER0 Register (Offset = 180h) [reset = X]1412.7.4.10 NVIC_ICER1 Register (Offset = 184h) [reset = X]1442.7.4.11 NVIC_ISPR0 Register (Offset = 200h) [reset = X]1452.7.4.12 NVIC_ISPR1 Register (Offset = 204h) [reset = X]1482.7.4.13 NVIC_ICPR0 Register (Offset = 280h) [reset = X]1492.7.4.14 NVIC_ICPR1 Register (Offset = 284h) [reset = X]1522.7.4.15 NVIC_IABR0 Register (Offset = 300h) [reset = X]1532.7.4.16 NVIC_IABR1 Register (Offset = 304h) [reset = X]1562.7.4.17 NVIC_IPR0 Register (Offset = 400h) [reset = X]1572.7.4.18 NVIC_IPR1 Register (Offset = 404h) [reset = X]1582.7.4.19 NVIC_IPR2 Register (Offset = 408h) [reset = X]1592.7.4.20 NVIC_IPR3 Register (Offset = 40Ch) [reset = X]1602.7.4.21 NVIC_IPR4 Register (Offset = 410h) [reset = X]1612.7.4.22 NVIC_IPR5 Register (Offset = 414h) [reset = X]1622.7.4.23 NVIC_IPR6 Register (Offset = 418h) [reset = X]1632.7.4.24 NVIC_IPR7 Register (Offset = 41Ch) [reset = X]1642.7.4.25 NVIC_IPR8 Register (Offset = 420h) [reset = X]1652.7.4.26 CPUID Register (Offset = D00h) [reset = 412FC231h]1662.7.4.27 ICSR Register (Offset = D04h) [reset = X]1672.7.4.28 VTOR Register (Offset = D08h) [reset = X]1682.7.4.29 AIRCR Register (Offset = D0Ch) [reset = X]1692.7.4.30 SCR Register (Offset = D10h) [reset = X]1702.7.4.31 CCR Register (Offset = D14h) [reset = X]1712.7.4.32 SHPR1 Register (Offset = D18h) [reset = X]1732.7.4.33 SHPR2 Register (Offset = D1Ch) [reset = X]1742.7.4.34 SHPR3 Register (Offset = D20h) [reset = X]1752.7.4.35 SHCSR Register (Offset = D24h) [reset = X]1762.7.4.36 CFSR Register (Offset = D28h) [reset = X]1782.7.4.37 HFSR Register (Offset = D2Ch) [reset = X]1802.7.4.38 DFSR Register (Offset = D30h) [reset = X]1812.7.4.39 MMFAR Register (Offset = D34h) [reset = 0h]1822.7.4.40 BFAR Register (Offset = D38h) [reset = 0h]1832.7.4.41 AFSR Register (Offset = D3Ch) [reset = X]1842.7.4.42 ID_PFR0 Register (Offset = D40h) [reset = X]1852.7.4.43 ID_PFR1 Register (Offset = D44h) [reset = X]1862.7.4.44 ID_DFR0 Register (Offset = D48h) [reset = X]1872.7.4.45 ID_AFR0 Register (Offset = D4Ch) [reset = X]1882.7.4.46 ID_MMFR0 Register (Offset = D50h) [reset = 100030h]1892.7.4.47 ID_MMFR1 Register (Offset = D54h) [reset = X]1902.7.4.48 ID_MMFR2 Register (Offset = D58h) [reset = X]1912.7.4.49 ID_MMFR3 Register (Offset = D5Ch) [reset = X]1922.7.4.50 ID_ISAR0 Register (Offset = D60h) [reset = 1101110h]1932.7.4.51 ID_ISAR1 Register (Offset = D64h) [reset = 2111000h]1942.7.4.52 ID_ISAR2 Register (Offset = D68h) [reset = 21112231h]1952.7.4.53 ID_ISAR3 Register (Offset = D6Ch) [reset = 1111110h]1962.7.4.54 ID_ISAR4 Register (Offset = D70h) [reset = 1310132h]1972.7.4.55 CPACR Register (Offset = D88h) [reset = X]1982.7.4.56 DHCSR Register (Offset = DF0h) [reset = X]1992.7.4.57 DCRSR Register (Offset = DF4h) [reset = 0h]2012.7.4.58 DCRDR Register (Offset = DF8h) [reset = 0h]2022.7.4.59 DEMCR Register (Offset = DFCh) [reset = X]2032.7.4.60 STIR Register (Offset = F00h) [reset = X]2052.7.5 CPU_TPIU Registers2072.7.5.1 SSPSR Register (Offset = 0h) [reset = X]2082.7.5.2 CSPSR Register (Offset = 4h) [reset = X]2092.7.5.3 ACPR Register (Offset = 10h) [reset = X]2102.7.5.4 SPPR Register (Offset = F0h) [reset = X]2112.7.5.5 FFSR Register (Offset = 300h) [reset = X]2122.7.5.6 FFCR Register (Offset = 304h) [reset = X]2132.7.5.7 FSCR Register (Offset = 308h) [reset = X]2142.7.5.8 CLAIMMASK Register (Offset = FA0h) [reset = Fh]2152.7.5.9 CLAIMSET Register (Offset = FA0h) [reset = Fh]2162.7.5.10 CLAIMTAG Register (Offset = FA4h) [reset = X]2172.7.5.11 CLAIMCLR Register (Offset = FA4h) [reset = X]2182.7.5.12 DEVID Register (Offset = FC8h) [reset = CA0h]2193 Cortex™-M3 Peripherals2203.1 Cortex™-M3 Peripherals Introduction2213.2 Functional Description2213.2.1 SysTick2213.2.2 NVIC2223.2.2.1 Level-Sensitive and Pulse Interrupts2223.2.2.2 Hardware and Software Control of Interrupts2233.2.3 System Control Block (SCB)2233.2.4 Instrumentation Trace Macrocell Unit (ITM)2233.2.5 Flash Patch and Breakpoint Unit (FPB)2233.2.6 Trace Port Interface Unit (TPIU)2243.2.7 Data Watchpoint and Trace Unit (DWT)2244 Interrupts and Events2274.1 Exception Model2284.1.1 Exception States2284.1.2 Exception Types2284.1.3 Exception Handlers2314.1.4 Vector Table2314.1.5 Exception Priorities2324.1.6 Interrupt Priority Grouping2324.1.7 Exception Entry and Return2334.1.7.1 Exception Entry2344.1.7.2 Exception Return2344.2 Fault Handling2354.2.1 Fault Types2354.2.2 Fault Escalation and Hard Faults2364.2.3 Fault Status Registers and Fault Address Registers2364.2.4 Lockup2364.3 Event Fabric2374.3.1 Introduction2374.3.2 Event Fabric Overview2384.3.2.1 Registers2384.4 AON Event Fabric2384.4.1 Common Input Event List2394.4.2 Event Subscribers2394.4.2.1 Wake-up Controller (WUC)2394.4.2.2 Real-Time Clock2404.4.2.3 MCU Event Fabric2404.5 MCU Event Fabric2404.5.1 Common Input Event List2414.5.2 Event Subscribers2444.5.2.1 System CPU2454.5.2.2 NMI2454.5.2.3 Freeze2454.6 Interrupts and Events Registers2454.6.1 AON_EVENT Registers2464.6.1.1 MCUWUSEL Register (Offset = 0h) [reset = X]2474.6.1.2 AUXWUSEL Register (Offset = 4h) [reset = X]2544.6.1.3 EVTOMCUSEL Register (Offset = 8h) [reset = X]2604.6.1.4 RTCSEL Register (Offset = Ch) [reset = X]2664.6.2 EVENT Registers2704.6.2.1 CPUIRQSEL0 Register (Offset = 0h) [reset = X]2734.6.2.2 CPUIRQSEL1 Register (Offset = 4h) [reset = X]2744.6.2.3 CPUIRQSEL2 Register (Offset = 8h) [reset = X]2754.6.2.4 CPUIRQSEL3 Register (Offset = Ch) [reset = X]2764.6.2.5 CPUIRQSEL4 Register (Offset = 10h) [reset = X]2774.6.2.6 CPUIRQSEL5 Register (Offset = 14h) [reset = X]2784.6.2.7 CPUIRQSEL6 Register (Offset = 18h) [reset = X]2794.6.2.8 CPUIRQSEL7 Register (Offset = 1Ch) [reset = X]2804.6.2.9 CPUIRQSEL8 Register (Offset = 20h) [reset = X]2814.6.2.10 CPUIRQSEL9 Register (Offset = 24h) [reset = X]2824.6.2.11 CPUIRQSEL10 Register (Offset = 28h) [reset = X]2834.6.2.12 CPUIRQSEL11 Register (Offset = 2Ch) [reset = X]2844.6.2.13 CPUIRQSEL12 Register (Offset = 30h) [reset = X]2854.6.2.14 CPUIRQSEL13 Register (Offset = 34h) [reset = X]2864.6.2.15 CPUIRQSEL14 Register (Offset = 38h) [reset = X]2874.6.2.16 CPUIRQSEL15 Register (Offset = 3Ch) [reset = X]2884.6.2.17 CPUIRQSEL16 Register (Offset = 40h) [reset = X]2894.6.2.18 CPUIRQSEL17 Register (Offset = 44h) [reset = X]2904.6.2.19 CPUIRQSEL18 Register (Offset = 48h) [reset = X]2914.6.2.20 CPUIRQSEL19 Register (Offset = 4Ch) [reset = X]2924.6.2.21 CPUIRQSEL20 Register (Offset = 50h) [reset = X]2934.6.2.22 CPUIRQSEL21 Register (Offset = 54h) [reset = X]2944.6.2.23 CPUIRQSEL22 Register (Offset = 58h) [reset = X]2954.6.2.24 CPUIRQSEL23 Register (Offset = 5Ch) [reset = X]2964.6.2.25 CPUIRQSEL24 Register (Offset = 60h) [reset = X]2974.6.2.26 CPUIRQSEL25 Register (Offset = 64h) [reset = X]2984.6.2.27 CPUIRQSEL26 Register (Offset = 68h) [reset = X]2994.6.2.28 CPUIRQSEL27 Register (Offset = 6Ch) [reset = X]3004.6.2.29 CPUIRQSEL28 Register (Offset = 70h) [reset = X]3014.6.2.30 CPUIRQSEL29 Register (Offset = 74h) [reset = X]3024.6.2.31 CPUIRQSEL30 Register (Offset = 78h) [reset = X]3034.6.2.32 CPUIRQSEL31 Register (Offset = 7Ch) [reset = X]3044.6.2.33 CPUIRQSEL32 Register (Offset = 80h) [reset = X]3054.6.2.34 CPUIRQSEL33 Register (Offset = 84h) [reset = X]3064.6.2.35 RFCSEL0 Register (Offset = 100h) [reset = X]3074.6.2.36 RFCSEL1 Register (Offset = 104h) [reset = X]3084.6.2.37 RFCSEL2 Register (Offset = 108h) [reset = X]3094.6.2.38 RFCSEL3 Register (Offset = 10Ch) [reset = X]3104.6.2.39 RFCSEL4 Register (Offset = 110h) [reset = X]3114.6.2.40 RFCSEL5 Register (Offset = 114h) [reset = X]3124.6.2.41 RFCSEL6 Register (Offset = 118h) [reset = X]3134.6.2.42 RFCSEL7 Register (Offset = 11Ch) [reset = X]3144.6.2.43 RFCSEL8 Register (Offset = 120h) [reset = X]3154.6.2.44 RFCSEL9 Register (Offset = 124h) [reset = X]3164.6.2.45 GPT0ACAPTSEL Register (Offset = 200h) [reset = X]3174.6.2.46 GPT0BCAPTSEL Register (Offset = 204h) [reset = X]3204.6.2.47 GPT1ACAPTSEL Register (Offset = 300h) [reset = X]3234.6.2.48 GPT1BCAPTSEL Register (Offset = 304h) [reset = X]3264.6.2.49 GPT2ACAPTSEL Register (Offset = 400h) [reset = X]3294.6.2.50 GPT2BCAPTSEL Register (Offset = 404h) [reset = X]3324.6.2.51 UDMACH1SSEL Register (Offset = 508h) [reset = X]3354.6.2.52 UDMACH1BSEL Register (Offset = 50Ch) [reset = X]3364.6.2.53 UDMACH2SSEL Register (Offset = 510h) [reset = X]3374.6.2.54 UDMACH2BSEL Register (Offset = 514h) [reset = X]3384.6.2.55 UDMACH3SSEL Register (Offset = 518h) [reset = X]3394.6.2.56 UDMACH3BSEL Register (Offset = 51Ch) [reset = X]3404.6.2.57 UDMACH4SSEL Register (Offset = 520h) [reset = X]3414.6.2.58 UDMACH4BSEL Register (Offset = 524h) [reset = X]3424.6.2.59 UDMACH5SSEL Register (Offset = 528h) [reset = X]3434.6.2.60 UDMACH5BSEL Register (Offset = 52Ch) [reset = X]3444.6.2.61 UDMACH6SSEL Register (Offset = 530h) [reset = X]3454.6.2.62 UDMACH6BSEL Register (Offset = 534h) [reset = X]3464.6.2.63 UDMACH7SSEL Register (Offset = 538h) [reset = X]3474.6.2.64 UDMACH7BSEL Register (Offset = 53Ch) [reset = X]3484.6.2.65 UDMACH8SSEL Register (Offset = 540h) [reset = X]3494.6.2.66 UDMACH8BSEL Register (Offset = 544h) [reset = X]3504.6.2.67 UDMACH9SSEL Register (Offset = 548h) [reset = X]3514.6.2.68 UDMACH9BSEL Register (Offset = 54Ch) [reset = X]3524.6.2.69 UDMACH10SSEL Register (Offset = 550h) [reset = X]3534.6.2.70 UDMACH10BSEL Register (Offset = 554h) [reset = X]3544.6.2.71 UDMACH11SSEL Register (Offset = 558h) [reset = X]3554.6.2.72 UDMACH11BSEL Register (Offset = 55Ch) [reset = X]3564.6.2.73 UDMACH12SSEL Register (Offset = 560h) [reset = X]3574.6.2.74 UDMACH12BSEL Register (Offset = 564h) [reset = X]3584.6.2.75 UDMACH13BSEL Register (Offset = 56Ch) [reset = X]3594.6.2.76 UDMACH14BSEL Register (Offset = 574h) [reset = X]3604.6.2.77 UDMACH15BSEL Register (Offset = 57Ch) [reset = X]3654.6.2.78 UDMACH16SSEL Register (Offset = 580h) [reset = X]3664.6.2.79 UDMACH16BSEL Register (Offset = 584h) [reset = X]3674.6.2.80 UDMACH17SSEL Register (Offset = 588h) [reset = X]3684.6.2.81 UDMACH17BSEL Register (Offset = 58Ch) [reset = X]3694.6.2.82 UDMACH21SSEL Register (Offset = 5A8h) [reset = X]3704.6.2.83 UDMACH21BSEL Register (Offset = 5ACh) [reset = X]3714.6.2.84 UDMACH22SSEL Register (Offset = 5B0h) [reset = X]3724.6.2.85 UDMACH22BSEL Register (Offset = 5B4h) [reset = X]3734.6.2.86 UDMACH23SSEL Register (Offset = 5B8h) [reset = X]3744.6.2.87 UDMACH23BSEL Register (Offset = 5BCh) [reset = X]3754.6.2.88 UDMACH24SSEL Register (Offset = 5C0h) [reset = X]3764.6.2.89 UDMACH24BSEL Register (Offset = 5C4h) [reset = X]3774.6.2.90 GPT3ACAPTSEL Register (Offset = 600h) [reset = X]3784.6.2.91 GPT3BCAPTSEL Register (Offset = 604h) [reset = X]3814.6.2.92 AUXSEL0 Register (Offset = 700h) [reset = X]3844.6.2.93 CM3NMISEL0 Register (Offset = 800h) [reset = X]3854.6.2.94 I2SSTMPSEL0 Register (Offset = 900h) [reset = X]3864.6.2.95 FRZSEL0 Register (Offset = A00h) [reset = X]3874.6.2.96 SWEV Register (Offset = F00h) [reset = X]3885 JTAG Interface3895.1 Top Level Debug System3905.2 cJTAG3925.2.1 JTAG Commands3945.2.1.1 Mandatory Commands3965.2.2 Programming Sequences3965.2.2.1 Opening Command Window3965.2.2.2 Changing to 4-pin Mode3965.2.2.3 Close Command Window3975.3 ICEPick™3975.3.1 Secondary TAPs3975.3.1.1 Slave DAP (CPU DAP)3985.3.1.2 Ordering Slave TAPs and DAPs3985.3.2 ICEPick™ Registers3995.3.2.1 IR Instructions3995.3.2.2 Data Shift Register4005.3.2.3 Instruction Register4005.3.2.4 Bypass Register4005.3.2.5 Device Identification Register4005.3.2.6 User Code Register4015.3.2.7 ICEPick™ Identification Register4015.3.2.8 Connect Register4025.3.3 ROUTER Scan Chain4025.3.4 TAP Routing Registers4035.3.4.1 ICEPick™ Control Block4035.3.4.1.1 All0s Register4045.3.4.1.2 ICEPick™ Control Register4045.3.4.1.3 Linking Mode Register4045.3.4.2 Test TAP Linking Block4055.3.4.2.1 Secondary Test TAP Register4055.3.4.3 Debug TAP Linking Block4055.3.4.3.1 Secondary Debug TAP Register4055.4 ICEMelter™4085.5 Serial Wire Viewer (SWV)4085.6 Halt In Boot (HIB)4085.7 Debug and Shutdown4095.8 Debug Features Supported Through WUC TAP4095.9 Profiler Register4096 Power, Reset, and Clock Management4116.1 Introduction4126.1.1 System CPU Mode4136.1.2 Supply System4136.1.2.1 Internal DC-DC Converter and Global LDO4146.1.2.2 External Regulator Mode4156.1.3 Digital Power Partitioning4156.1.3.1 MCU_VD4176.1.3.1.1 MCU_VD Power Domains4176.1.3.2 AON_VD4176.1.3.2.1 AON_VD Power Domains4176.1.4 Clock Management4176.1.4.1 System Clocks4176.1.4.1.1 Controlling the Oscillators4186.1.4.2 Clocks in MCU_VD4206.1.4.2.1 Clock Gating4226.1.4.2.2 Scalar to GPT4226.1.4.2.3 Scalar to WDT4226.1.4.3 Clocks in AON_VD4226.1.5 Power Modes4226.1.5.1 Startup State4236.1.5.2 Active Mode4246.1.5.3 Idle Mode4246.1.5.4 Standby Mode4246.1.5.5 Shutdown Mode4256.1.6 Reset4266.1.6.1 System Resets4266.1.6.1.1 Clock Loss Detection4266.1.6.1.2 Software-Initiated System Reset4266.1.6.1.3 Warm Reset Converted to System Reset4266.1.6.2 Warm Reset4266.1.6.3 Software-Initiated Reset of MCU_VD4276.1.6.4 Reset of the MCU_VD Power Domains and Modules4276.1.6.5 Reset of AON_VD4276.1.6.6 Reset of AUX_PD4276.2 PRCM Registers4276.2.1 PRCM Registers4286.2.1.1 INFRCLKDIVR Register (Offset = 0h) [reset = X]4306.2.1.2 INFRCLKDIVS Register (Offset = 4h) [reset = X]4316.2.1.3 INFRCLKDIVDS Register (Offset = 8h) [reset = X]4326.2.1.4 VDCTL Register (Offset = Ch) [reset = X]4336.2.1.5 CLKLOADCTL Register (Offset = 28h) [reset = X]4346.2.1.6 RFCCLKG Register (Offset = 2Ch) [reset = X]4356.2.1.7 VIMSCLKG Register (Offset = 30h) [reset = X]4366.2.1.8 SECDMACLKGR Register (Offset = 3Ch) [reset = X]4376.2.1.9 SECDMACLKGS Register (Offset = 40h) [reset = X]4386.2.1.10 SECDMACLKGDS Register (Offset = 44h) [reset = X]4396.2.1.11 GPIOCLKGR Register (Offset = 48h) [reset = X]4406.2.1.12 GPIOCLKGS Register (Offset = 4Ch) [reset = X]4416.2.1.13 GPIOCLKGDS Register (Offset = 50h) [reset = X]4426.2.1.14 GPTCLKGR Register (Offset = 54h) [reset = X]4436.2.1.15 GPTCLKGS Register (Offset = 58h) [reset = X]4446.2.1.16 GPTCLKGDS Register (Offset = 5Ch) [reset = X]4456.2.1.17 I2CCLKGR Register (Offset = 60h) [reset = X]4466.2.1.18 I2CCLKGS Register (Offset = 64h) [reset = X]4476.2.1.19 I2CCLKGDS Register (Offset = 68h) [reset = X]4486.2.1.20 UARTCLKGR Register (Offset = 6Ch) [reset = X]4496.2.1.21 UARTCLKGS Register (Offset = 70h) [reset = X]4506.2.1.22 UARTCLKGDS Register (Offset = 74h) [reset = X]4516.2.1.23 SSICLKGR Register (Offset = 78h) [reset = X]4526.2.1.24 SSICLKGS Register (Offset = 7Ch) [reset = X]4536.2.1.25 SSICLKGDS Register (Offset = 80h) [reset = X]4546.2.1.26 I2SCLKGR Register (Offset = 84h) [reset = X]4556.2.1.27 I2SCLKGS Register (Offset = 88h) [reset = X]4566.2.1.28 I2SCLKGDS Register (Offset = 8Ch) [reset = X]4576.2.1.29 CPUCLKDIV Register (Offset = B8h) [reset = X]4586.2.1.30 I2SBCLKSEL Register (Offset = C8h) [reset = X]4596.2.1.31 GPTCLKDIV Register (Offset = CCh) [reset = X]4606.2.1.32 I2SCLKCTL Register (Offset = D0h) [reset = X]4616.2.1.33 I2SMCLKDIV Register (Offset = D4h) [reset = X]4626.2.1.34 I2SBCLKDIV Register (Offset = D8h) [reset = X]4636.2.1.35 I2SWCLKDIV Register (Offset = DCh) [reset = X]4646.2.1.36 SWRESET Register (Offset = 10Ch) [reset = X]4656.2.1.37 WARMRESET Register (Offset = 110h) [reset = X]4666.2.1.38 PDCTL0 Register (Offset = 12Ch) [reset = X]4676.2.1.39 PDCTL0RFC Register (Offset = 130h) [reset = X]4686.2.1.40 PDCTL0SERIAL Register (Offset = 134h) [reset = X]4696.2.1.41 PDCTL0PERIPH Register (Offset = 138h) [reset = X]4706.2.1.42 PDSTAT0 Register (Offset = 140h) [reset = X]4716.2.1.43 PDSTAT0RFC Register (Offset = 144h) [reset = X]4726.2.1.44 PDSTAT0SERIAL Register (Offset = 148h) [reset = X]4736.2.1.45 PDSTAT0PERIPH Register (Offset = 14Ch) [reset = X]4746.2.1.46 PDCTL1 Register (Offset = 17Ch) [reset = X]4756.2.1.47 PDCTL1CPU Register (Offset = 184h) [reset = X]4766.2.1.48 PDCTL1RFC Register (Offset = 188h) [reset = X]4776.2.1.49 PDCTL1VIMS Register (Offset = 18Ch) [reset = X]4786.2.1.50 PDSTAT1 Register (Offset = 194h) [reset = X]4796.2.1.51 PDSTAT1BUS Register (Offset = 198h) [reset = X]4806.2.1.52 PDSTAT1RFC Register (Offset = 19Ch) [reset = X]4816.2.1.53 PDSTAT1CPU Register (Offset = 1A0h) [reset = X]4826.2.1.54 PDSTAT1VIMS Register (Offset = 1A4h) [reset = X]4836.2.1.55 RFCMODESEL Register (Offset = 1D0h) [reset = X]4846.2.1.56 RAMRETEN Register (Offset = 224h) [reset = X]4856.2.1.57 RAMHWOPT Register (Offset = 250h) [reset = X]4866.2.2 AON_SYSCTL Registers4886.2.2.1 PWRCTL Register (Offset = 0h) [reset = X]4896.2.2.2 RESETCTL Register (Offset = 4h) [reset = X]4906.2.2.3 SLEEPCTL Register (Offset = 8h) [reset = X]4926.2.3 AON_WUC Registers4936.2.3.1 MCUCLK Register (Offset = 0h) [reset = X]4946.2.3.2 AUXCLK Register (Offset = 4h) [reset = X]4956.2.3.3 MCUCFG Register (Offset = 8h) [reset = X]4966.2.3.4 AUXCFG Register (Offset = Ch) [reset = X]4976.2.3.5 AUXCTL Register (Offset = 10h) [reset = X]4986.2.3.6 PWRSTAT Register (Offset = 14h) [reset = X]4996.2.3.7 SHUTDOWN Register (Offset = 18h) [reset = X]5006.2.3.8 CTL0 Register (Offset = 20h) [reset = X]5016.2.3.9 CTL1 Register (Offset = 24h) [reset = X]5026.2.3.10 RECHARGECFG Register (Offset = 30h) [reset = X]5036.2.3.11 RECHARGESTAT Register (Offset = 34h) [reset = X]5056.2.3.12 OSCCFG Register (Offset = 38h) [reset = X]5066.2.3.13 JTAGCFG Register (Offset = 40h) [reset = X]5076.2.3.14 JTAGUSERCODE Register (Offset = 44h) [reset = B99A02Fh]5086.2.4 DDI_0_OSC Registers5096.2.4.1 CTL0 Register (Offset = 0h) [reset = X]5106.2.4.2 CTL1 Register (Offset = 4h) [reset = X]5126.2.4.3 RADCEXTCFG Register (Offset = 8h) [reset = X]5136.2.4.4 AMPCOMPCTL Register (Offset = Ch) [reset = X]5146.2.4.5 AMPCOMPTH1 Register (Offset = 10h) [reset = X]5156.2.4.6 AMPCOMPTH2 Register (Offset = 14h) [reset = X]5166.2.4.7 ANABYPASSVAL1 Register (Offset = 18h) [reset = X]5176.2.4.8 ANABYPASSVAL2 Register (Offset = 1Ch) [reset = X]5186.2.4.9 ATESTCTL Register (Offset = 20h) [reset = X]5196.2.4.10 ADCDOUBLERNANOAMPCTL Register (Offset = 24h) [reset = X]5206.2.4.11 XOSCHFCTL Register (Offset = 28h) [reset = X]5216.2.4.12 LFOSCCTL Register (Offset = 2Ch) [reset = X]5226.2.4.13 RCOSCHFCTL Register (Offset = 30h) [reset = X]5236.2.4.14 STAT0 Register (Offset = 34h) [reset = X]5246.2.4.15 STAT1 Register (Offset = 38h) [reset = X]5266.2.4.16 STAT2 Register (Offset = 3Ch) [reset = X]5287 Versatile Instruction Memory System (VIMS)5297.1 VIMS Configurations5317.1.1 VIMS Modes5317.1.1.1 GPRAM Mode5317.1.1.2 Off Mode5327.1.1.3 Cache Mode5327.1.1.4 Split Mode5337.1.2 VIMS Flash Line Buffering5347.1.3 VIMS Arbitration5347.1.4 VIMS Cache TAG Prefetch5347.2 VIMS Software (SW) Remarks5347.2.1 Flash Program or Update5347.2.2 VIMS Retention5347.2.2.1 Mode 15357.2.2.2 Mode 25357.3 VIMS Registers5377.3.1 STAT Register (Offset = 0h) [reset = X]5387.3.2 CTL Register (Offset = 4h) [reset = X]5397.4 ROM5407.5 EEFUSE5407.6 FLASH5407.6.1 FLASH Memory Protection5407.6.2 Memory Programming5407.6.2.1 Disabling Debug Access5417.6.3 FLASH Memory Programming5417.6.4 FLASH Read Timings5417.6.5 Power Mode Operations5417.7 VIMS Registers5417.7.1 FLASHMEM Registers5427.7.2 FLASH Registers5437.7.2.1 STAT Register (Offset = 1Ch) [reset = X]5467.7.2.2 CFG Register (Offset = 24h) [reset = X]5477.7.2.3 SYSCODE_START Register (Offset = 28h) [reset = X]5487.7.2.4 FLASH_SIZE Register (Offset = 2Ch) [reset = X]5497.7.2.5 FWLOCK Register (Offset = 3Ch) [reset = X]5507.7.2.6 FWFLAG Register (Offset = 40h) [reset = X]5517.7.2.7 EFUSE Register (Offset = 1000h) [reset = X]5527.7.2.8 EFUSEADDR Register (Offset = 1004h) [reset = X]5537.7.2.9 DATAUPPER Register (Offset = 1008h) [reset = X]5547.7.2.10 DATALOWER Register (Offset = 100Ch) [reset = X]5557.7.2.11 EFUSECFG Register (Offset = 1010h) [reset = X]5567.7.2.12 EFUSESTAT Register (Offset = 1014h) [reset = X]5577.7.2.13 ACC Register (Offset = 1018h) [reset = X]5587.7.2.14 BOUNDARY Register (Offset = 101Ch) [reset = X]5597.7.2.15 EFUSEFLAG Register (Offset = 1020h) [reset = X]5607.7.2.16 EFUSEKEY Register (Offset = 1024h) [reset = X]5617.7.2.17 EFUSERELEASE Register (Offset = 1028h) [reset = 0h]5627.7.2.18 EFUSEPINS Register (Offset = 102Ch) [reset = X]5637.7.2.19 EFUSECRA Register (Offset = 1030h) [reset = X]5647.7.2.20 EFUSEREAD Register (Offset = 1034h) [reset = X]5657.7.2.21 EFUSEPROGRAM Register (Offset = 1038h) [reset = X]5667.7.2.22 EFUSEERROR Register (Offset = 103Ch) [reset = X]5677.7.2.23 SINGLEBIT Register (Offset = 1040h) [reset = X]5687.7.2.24 TWOBIT Register (Offset = 1044h) [reset = X]5697.7.2.25 SELFTESTCYC Register (Offset = 1048h) [reset = X]5707.7.2.26 SELFTESTSIGN Register (Offset = 104Ch) [reset = X]5717.7.2.27 FRDCTL Register (Offset = 2000h) [reset = X]5727.7.2.28 FSPRD Register (Offset = 2004h) [reset = X]5737.7.2.29 FEDACCTL1 Register (Offset = 2008h) [reset = X]5747.7.2.30 FEDACSTAT Register (Offset = 201Ch) [reset = X]5757.7.2.31 FBPROT Register (Offset = 2030h) [reset = X]5767.7.2.32 FBSE Register (Offset = 2034h) [reset = X]5777.7.2.33 FBBUSY Register (Offset = 2038h) [reset = X]5787.7.2.34 FBAC Register (Offset = 203Ch) [reset = X]5797.7.2.35 FBFALLBACK Register (Offset = 2040h) [reset = X]5807.7.2.36 FBPRDY Register (Offset = 2044h) [reset = X]5817.7.2.37 FPAC1 Register (Offset = 2048h) [reset = X]5827.7.2.38 FPAC2 Register (Offset = 204Ch) [reset = X]5837.7.2.39 FMAC Register (Offset = 2050h) [reset = X]5847.7.2.40 FMSTAT Register (Offset = 2054h) [reset = X]5857.7.2.41 FLOCK Register (Offset = 2064h) [reset = X]5867.7.2.42 FVREADCT Register (Offset = 2080h) [reset = X]5877.7.2.43 FVHVCT1 Register (Offset = 2084h) [reset = X]5887.7.2.44 FVHVCT2 Register (Offset = 2088h) [reset = X]5897.7.2.45 FVHVCT3 Register (Offset = 208Ch) [reset = X]5907.7.2.46 FVNVCT Register (Offset = 2090h) [reset = X]5917.7.2.47 FVSLP Register (Offset = 2094h) [reset = X]5927.7.2.48 FVWLCT Register (Offset = 2098h) [reset = X]5937.7.2.49 FEFUSECTL Register (Offset = 209Ch) [reset = X]5947.7.2.50 FEFUSESTAT Register (Offset = 20A0h) [reset = X]5957.7.2.51 FEFUSEDATA Register (Offset = 20A4h) [reset = X]5967.7.2.52 FSEQPMP Register (Offset = 20A8h) [reset = X]5977.7.2.53 FBSTROBES Register (Offset = 2100h) [reset = X]5987.7.2.54 FPSTROBES Register (Offset = 2104h) [reset = X]5997.7.2.55 FBMODE Register (Offset = 2108h) [reset = X]6007.7.2.56 FTCR Register (Offset = 210Ch) [reset = X]6017.7.2.57 FADDR Register (Offset = 2110h) [reset = X]6027.7.2.58 FTCTL Register (Offset = 211Ch) [reset = X]6037.7.2.59 FWPWRITE0 Register (Offset = 2120h) [reset = FFFFFFFFh]6047.7.2.60 FWPWRITE1 Register (Offset = 2124h) [reset = FFFFFFFFh]6057.7.2.61 FWPWRITE2 Register (Offset = 2128h) [reset = FFFFFFFFh]6067.7.2.62 FWPWRITE3 Register (Offset = 212Ch) [reset = FFFFFFFFh]6077.7.2.63 FWPWRITE4 Register (Offset = 2130h) [reset = FFFFFFFFh]6087.7.2.64 FWPWRITE5 Register (Offset = 2134h) [reset = FFFFFFFFh]6097.7.2.65 FWPWRITE6 Register (Offset = 2138h) [reset = FFFFFFFFh]6107.7.2.66 FWPWRITE7 Register (Offset = 213Ch) [reset = FFFFFFFFh]6117.7.2.67 FWPWRITE_ECC Register (Offset = 2140h) [reset = FFFFFFFFh]6127.7.2.68 FSWSTAT Register (Offset = 2144h) [reset = X]6137.7.2.69 FSM_GLBCTL Register (Offset = 2200h) [reset = X]6147.7.2.70 FSM_STATE Register (Offset = 2204h) [reset = X]6157.7.2.71 FSM_STAT Register (Offset = 2208h) [reset = X]6167.7.2.72 FSM_CMD Register (Offset = 220Ch) [reset = X]6177.7.2.73 FSM_PE_OSU Register (Offset = 2210h) [reset = X]6187.7.2.74 FSM_VSTAT Register (Offset = 2214h) [reset = X]6197.7.2.75 FSM_PE_VSU Register (Offset = 2218h) [reset = X]6207.7.2.76 FSM_CMP_VSU Register (Offset = 221Ch) [reset = X]6217.7.2.77 FSM_EX_VAL Register (Offset = 2220h) [reset = X]6227.7.2.78 FSM_RD_H Register (Offset = 2224h) [reset = X]6237.7.2.79 FSM_P_OH Register (Offset = 2228h) [reset = X]6247.7.2.80 FSM_ERA_OH Register (Offset = 222Ch) [reset = X]6257.7.2.81 FSM_SAV_PPUL Register (Offset = 2230h) [reset = X]6267.7.2.82 FSM_PE_VH Register (Offset = 2234h) [reset = X]6277.7.2.83 FSM_PRG_PW Register (Offset = 2240h) [reset = X]6287.7.2.84 FSM_ERA_PW Register (Offset = 2244h) [reset = X]6297.7.2.85 FSM_SAV_ERA_PUL Register (Offset = 2254h) [reset = X]6307.7.2.86 FSM_TIMER Register (Offset = 2258h) [reset = X]6317.7.2.87 FSM_MODE Register (Offset = 225Ch) [reset = X]6327.7.2.88 FSM_PGM Register (Offset = 2260h) [reset = X]6337.7.2.89 FSM_ERA Register (Offset = 2264h) [reset = X]6347.7.2.90 FSM_PRG_PUL Register (Offset = 2268h) [reset = X]6357.7.2.91 FSM_ERA_PUL Register (Offset = 226Ch) [reset = X]6367.7.2.92 FSM_STEP_SIZE Register (Offset = 2270h) [reset = X]6377.7.2.93 FSM_PUL_CNTR Register (Offset = 2274h) [reset = X]6387.7.2.94 FSM_EC_STEP_HEIGHT Register (Offset = 2278h) [reset = X]6397.7.2.95 FSM_ST_MACHINE Register (Offset = 227Ch) [reset = X]6407.7.2.96 FSM_FLES Register (Offset = 2280h) [reset = X]6417.7.2.97 FSM_WR_ENA Register (Offset = 2288h) [reset = X]6427.7.2.98 FSM_ACC_PP Register (Offset = 228Ch) [reset = X]6437.7.2.99 FSM_ACC_EP Register (Offset = 2290h) [reset = X]6447.7.2.100 FSM_ADDR Register (Offset = 22A0h) [reset = X]6457.7.2.101 FSM_SECTOR Register (Offset = 22A4h) [reset = X]6467.7.2.102 FMC_REV_ID Register (Offset = 22A8h) [reset = 0h]6477.7.2.103 FSM_ERR_ADDR Register (Offset = 22ACh) [reset = X]6487.7.2.104 FSM_PGM_MAXPUL Register (Offset = 22B0h) [reset = X]6497.7.2.105 FSM_EXECUTE Register (Offset = 22B4h) [reset = X]6507.7.2.106 FSM_SECTOR1 Register (Offset = 22C0h) [reset = FFFFFFFFh]6517.7.2.107 FSM_SECTOR2 Register (Offset = 22C4h) [reset = X]6527.7.2.108 FSM_BSLE0 Register (Offset = 22E0h) [reset = X]6537.7.2.109 FSM_BSLE1 Register (Offset = 22E4h) [reset = X]6547.7.2.110 FSM_BSLP0 Register (Offset = 22F0h) [reset = X]6557.7.2.111 FSM_BSLP1 Register (Offset = 22F4h) [reset = X]6567.7.2.112 FCFG_BANK Register (Offset = 2400h) [reset = X]6577.7.2.113 FCFG_WRAPPER Register (Offset = 2404h) [reset = X]6587.7.2.114 FCFG_BNK_TYPE Register (Offset = 2408h) [reset = X]6597.7.2.115 FCFG_B0_START Register (Offset = 2410h) [reset = X]6607.7.2.116 FCFG_B1_START Register (Offset = 2414h) [reset = X]6617.7.2.117 FCFG_B2_START Register (Offset = 2418h) [reset = X]6627.7.2.118 FCFG_B3_START Register (Offset = 241Ch) [reset = X]6637.7.2.119 FCFG_B4_START Register (Offset = 2420h) [reset = X]6647.7.2.120 FCFG_B5_START Register (Offset = 2424h) [reset = X]6657.7.2.121 FCFG_B6_START Register (Offset = 2428h) [reset = X]6667.7.2.122 FCFG_B7_START Register (Offset = 242Ch) [reset = X]6677.7.2.123 FCFG_B0_SSIZE0 Register (Offset = 2430h) [reset = X]6687.8 ROM Functions6697.9 SRAM6708 Bootloader6718.1 Bootloader Functionality6728.1.1 Bootloader Disabling6728.1.2 Bootloader Backdoor6728.2 Bootloader Interfaces6728.2.1 Packet Handling6738.2.1.1 Packet Acknowledge and Not-Acknowledge Bytes6748.2.2 Transport Layer6748.2.2.1 UART Transport6758.2.2.1.1 UART Baud Rate Auto-Detection6758.2.2.2 SSI Transport6758.2.3 Serial Bus Commands6768.2.3.1 COMMAND_PING6778.2.3.2 COMMAND_DOWNLOAD6788.2.3.3 COMMAND_SEND_DATA6788.2.3.4 COMMAND_SECTOR_ERASE6788.2.3.5 COMMAND_GET_STATUS6798.2.3.6 COMMAND_RESET6808.2.3.7 COMMAND_GET_CHIP_ID6808.2.3.8 COMMAND_CRC326818.2.3.9 COMMAND_BANK_ERASE6828.2.3.10 COMMAND_CHIP_ERASE6828.2.3.11 COMMAND_SET_CCFG6829 Device Configuration6859.1 Customer Configuration (CCFG)6869.1.1 CCFG Registers6879.1.1.1 MODE_CONF_1 Register (Offset = FACh) [reset = FFFBFFFFh]6889.1.1.2 SIZE_AND_DIS_FLAGS Register (Offset = FB0h) [reset = FFFFFFFFh]6899.1.1.3 MODE_CONF Register (Offset = FB4h) [reset = FFFFFFFFh]6909.1.1.4 VOLT_LOAD_0 Register (Offset = FB8h) [reset = FFFFFFFFh]6929.1.1.5 VOLT_LOAD_1 Register (Offset = FBCh) [reset = FFFFFFFFh]6939.1.1.6 RTC_OFFSET Register (Offset = FC0h) [reset = FFFFFFFFh]6949.1.1.7 FREQ_OFFSET Register (Offset = FC4h) [reset = FFFFFFFFh]6959.1.1.8 IEEE_MAC_0 Register (Offset = FC8h) [reset = FFFFFFFFh]6969.1.1.9 IEEE_MAC_1 Register (Offset = FCCh) [reset = FFFFFFFFh]6979.1.1.10 IEEE_BLE_0 Register (Offset = FD0h) [reset = FFFFFFFFh]6989.1.1.11 IEEE_BLE_1 Register (Offset = FD4h) [reset = FFFFFFFFh]6999.1.1.12 BL_CONFIG Register (Offset = FD8h) [reset = C5FFFFFFh]7009.1.1.13 ERASE_CONF Register (Offset = FDCh) [reset = FFFFFFFFh]7019.1.1.14 CCFG_TI_OPTIONS Register (Offset = FE0h) [reset = FFFFFFC5h]7029.1.1.15 CCFG_TAP_DAP_0 Register (Offset = FE4h) [reset = FFC5C5C5h]7039.1.1.16 CCFG_TAP_DAP_1 Register (Offset = FE8h) [reset = FFC5C5C5h]7049.1.1.17 IMAGE_VALID_CONF Register (Offset = FECh) [reset = FFFFFFFFh]7059.1.1.18 CCFG_PROT_31_0 Register (Offset = FF0h) [reset = FFFFFFFFh]7069.1.1.19 CCFG_PROT_63_32 Register (Offset = FF4h) [reset = FFFFFFFFh]7089.1.1.20 CCFG_PROT_95_64 Register (Offset = FF8h) [reset = FFFFFFFFh]7109.1.1.21 CCFG_PROT_127_96 Register (Offset = FFCh) [reset = FFFFFFFFh]7129.2 Factory Configuration (FCFG)7139.2.1 FCFG1 Registers7149.2.1.1 CONFIG_RF_FRONTEND_DIV5 Register (Offset = C4h) [reset = FFFFFFFFh]7169.2.1.2 CONFIG_RF_FRONTEND_DIV6 Register (Offset = C8h) [reset = FFFFFFFFh]7179.2.1.3 CONFIG_RF_FRONTEND_DIV10 Register (Offset = CCh) [reset = FFFFFFFFh]7189.2.1.4 CONFIG_RF_FRONTEND_DIV12 Register (Offset = D0h) [reset = FFFFFFFFh]7199.2.1.5 CONFIG_RF_FRONTEND_DIV15 Register (Offset = D4h) [reset = FFFFFFFFh]7209.2.1.6 CONFIG_RF_FRONTEND_DIV30 Register (Offset = D8h) [reset = FFFFFFFFh]7219.2.1.7 CONFIG_SYNTH_DIV5 Register (Offset = DCh) [reset = FFFFFFFFh]7229.2.1.8 CONFIG_SYNTH_DIV6 Register (Offset = E0h) [reset = FFFFFFFFh]7239.2.1.9 CONFIG_SYNTH_DIV10 Register (Offset = E4h) [reset = FFFFFFFFh]7249.2.1.10 CONFIG_SYNTH_DIV12 Register (Offset = E8h) [reset = FFFFFFFFh]7259.2.1.11 CONFIG_SYNTH_DIV15 Register (Offset = ECh) [reset = FFFFFFFFh]7269.2.1.12 CONFIG_SYNTH_DIV30 Register (Offset = F0h) [reset = FFFFFFFFh]7279.2.1.13 CONFIG_MISC_ADC_DIV5 Register (Offset = F4h) [reset = FFFFFFFFh]7289.2.1.14 CONFIG_MISC_ADC_DIV6 Register (Offset = F8h) [reset = FFFFFFFFh]7299.2.1.15 CONFIG_MISC_ADC_DIV10 Register (Offset = FCh) [reset = FFFFFFFFh]7309.2.1.16 CONFIG_MISC_ADC_DIV12 Register (Offset = 100h) [reset = FFFFFFFFh]7319.2.1.17 CONFIG_MISC_ADC_DIV15 Register (Offset = 104h) [reset = FFFFFFFFh]7329.2.1.18 CONFIG_MISC_ADC_DIV30 Register (Offset = 108h) [reset = FFFFFFFFh]7339.2.1.19 SHDW_DIE_ID_0 Register (Offset = 118h) [reset = 0h]7349.2.1.20 SHDW_DIE_ID_1 Register (Offset = 11Ch) [reset = 0h]7359.2.1.21 SHDW_DIE_ID_2 Register (Offset = 120h) [reset = 0h]7369.2.1.22 SHDW_DIE_ID_3 Register (Offset = 124h) [reset = 0h]7379.2.1.23 SHDW_OSC_BIAS_LDO_TRIM Register (Offset = 138h) [reset = 0h]7389.2.1.24 SHDW_ANA_TRIM Register (Offset = 13Ch) [reset = 0h]7399.2.1.25 FLASH_NUMBER Register (Offset = 164h) [reset = 0h]7409.2.1.26 FLASH_COORDINATE Register (Offset = 16Ch) [reset = 0h]7419.2.1.27 FLASH_E_P Register (Offset = 170h) [reset = 17331A33h]7429.2.1.28 FLASH_C_E_P_R Register (Offset = 174h) [reset = X]7439.2.1.29 FLASH_P_R_PV Register (Offset = 178h) [reset = X]7449.2.1.30 FLASH_EH_SEQ Register (Offset = 17Ch) [reset = X]7459.2.1.31 FLASH_VHV_E Register (Offset = 180h) [reset = X]7469.2.1.32 FLASH_PP Register (Offset = 184h) [reset = X]7479.2.1.33 FLASH_PROG_EP Register (Offset = 188h) [reset = FA00010h]7489.2.1.34 FLASH_ERA_PW Register (Offset = 18Ch) [reset = FA0h]7499.2.1.35 FLASH_VHV Register (Offset = 190h) [reset = X]7509.2.1.36 FLASH_VHV_PV Register (Offset = 194h) [reset = X]7519.2.1.37 FLASH_V Register (Offset = 198h) [reset = 0h]7529.2.1.38 USER_ID Register (Offset = 294h) [reset = 0h]7539.2.1.39 FLASH_OTP_DATA3 Register (Offset = 2B0h) [reset = X]7549.2.1.40 ANA2_TRIM Register (Offset = 2B4h) [reset = X]7559.2.1.41 LDO_TRIM Register (Offset = 2B8h) [reset = X]7579.2.1.42 MAC_BLE_0 Register (Offset = 2E8h) [reset = 0h]7589.2.1.43 MAC_BLE_1 Register (Offset = 2ECh) [reset = 0h]7599.2.1.44 MAC_15_4_0 Register (Offset = 2F0h) [reset = 0h]7609.2.1.45 MAC_15_4_1 Register (Offset = 2F4h) [reset = 0h]7619.2.1.46 FLASH_OTP_DATA4 Register (Offset = 308h) [reset = X]7629.2.1.47 MISC_TRIM Register (Offset = 30Ch) [reset = FFFFFF33h]7649.2.1.48 RCOSC_HF_TEMPCOMP Register (Offset = 310h) [reset = X]7659.2.1.49 TRIM_CAL_REVISION Register (Offset = 314h) [reset = 0h]7669.2.1.50 ICEPICK_DEVICE_ID Register (Offset = 318h) [reset = 8B99A02Fh]7679.2.1.51 FCFG1_REVISION Register (Offset = 31Ch) [reset = 23h]7689.2.1.52 MISC_OTP_DATA Register (Offset = 320h) [reset = X]7699.2.1.53 IOCONF Register (Offset = 344h) [reset = 7FFFFF8000h]7709.2.1.54 CONFIG_IF_ADC Register (Offset = 34Ch) [reset = X]7719.2.1.55 CONFIG_OSC_TOP Register (Offset = 350h) [reset = X]7729.2.1.56 CONFIG_RF_FRONTEND Register (Offset = 354h) [reset = X]7739.2.1.57 CONFIG_SYNTH Register (Offset = 358h) [reset = FFFFF000h]7749.2.1.58 SOC_ADC_ABS_GAIN Register (Offset = 35Ch) [reset = 0h]7759.2.1.59 SOC_ADC_REL_GAIN Register (Offset = 360h) [reset = 0h]7769.2.1.60 SOC_ADC_EXT_GAIN Register (Offset = 364h) [reset = 0h]7779.2.1.61 SOC_ADC_OFFSET_INT Register (Offset = 368h) [reset = 0h]7789.2.1.62 SOC_ADC_REF_TRIM_AND_OFFSET_EXT Register (Offset = 36Ch) [reset = 300080h]7799.2.1.63 AMPCOMP_TH1 Register (Offset = 370h) [reset = FF7B828Eh]7809.2.1.64 AMPCOMP_TH2 Register (Offset = 374h) [reset = X]7819.2.1.65 AMPCOMP_CTRL1 Register (Offset = 378h) [reset = FF183F47h]7829.2.1.66 ANABYPASS_VALUE2 Register (Offset = 37Ch) [reset = FFFFC3FFh]7839.2.1.67 CONFIG_MISC_ADC Register (Offset = 380h) [reset = FFFC014Dh]7849.2.1.68 VOLT_TRIM Register (Offset = 388h) [reset = FFFFFFE0h]7859.2.1.69 OSC_CONF Register (Offset = 38Ch) [reset = X]7869.2.1.70 CAP_TRIM Register (Offset = 394h) [reset = FFFFFFFFh]7879.2.1.71 MISC_OTP_DATA_1 Register (Offset = 398h) [reset = X]7889.2.1.72 PWD_CURR_20C Register (Offset = 39Ch) [reset = 80BA608h]7899.2.1.73 PWD_CURR_35C Register (Offset = 3A0h) [reset = C10A50Ah]7909.2.1.74 PWD_CURR_50C Register (Offset = 3A4h) [reset = 1218A20Dh]7919.2.1.75 PWD_CURR_65C Register (Offset = 3A8h) [reset = 1C259C14h]7929.2.1.76 PWD_CURR_80C Register (Offset = 3ACh) [reset = 2E3B9021h]7939.2.1.77 PWD_CURR_95C Register (Offset = 3B0h) [reset = 4C627A3Bh]7949.2.1.78 PWD_CURR_110C Register (Offset = 3B4h) [reset = 789E706Bh]7959.2.1.79 PWD_CURR_125C Register (Offset = 3B8h) [reset = ADE1809Ah]79610 Cryptography79710.1 AES Cryptoprocessor Overview79810.1.1 Functional Description79810.1.1.1 Debug Capabilities79910.1.1.2 Exception Handling79910.1.2 Power Management and Sleep Modes79910.1.3 Hardware Description79910.1.3.1 AHB Slave Bus79910.1.3.2 AHB Master Bus79910.1.3.3 Interrupts80010.1.4 Module Description80010.1.4.1 Introduction80010.1.4.2 Module Memory Map80010.1.4.3 DMA Controller80210.1.4.3.1 Internal Operation80310.1.4.3.2 Supported DMA Operations80410.1.4.4 Master Control and Select80410.1.4.4.1 Algorithm Select80510.1.4.4.2 Master PROT Enable80510.1.4.4.3 Software Reset80510.1.4.5 AES Engine80510.1.4.5.1 Second Key Registers (internal, but clearable)80610.1.4.5.2 AES Initialization Vector (IV) Registers80710.1.4.5.3 AES I/O Buffer Control, Mode, and Length Registers80710.1.4.5.4 Data Input/Output Registers80810.1.4.5.5 TAG Registers80910.1.4.6 Key Area Registers80910.1.4.6.1 Key Write Area Register80910.1.4.6.2 Key Written Area Register80910.1.4.6.3 Key Size Register80910.1.4.6.4 Key Read Area Register81010.1.5 Performance81010.1.5.1 Introduction81010.1.5.2 Performance81110.1.6 Programming Guidelines81110.1.6.1 One Time Initialization After a Reset81110.1.6.2 DMAC and Master Control81110.1.6.2.1 Regular Use81110.1.6.2.2 Interrupting DMA Transfers81210.1.6.2.3 Interrupts and Harware and Software Synchronization81210.1.6.3 Encryption and Decryption81210.1.6.3.1 Data Format and Byte Order81310.1.6.3.2 Key Store81410.1.6.3.3 Basic AES Modes81410.1.6.3.4 CBC-MAC81710.1.6.3.5 AES-CCM81810.1.6.4 Exceptions Handling81910.1.6.4.1 Soft Reset81910.1.6.4.2 External Port Errors81910.1.6.4.3 Key Store Errors82010.1.7 Conventions and Compliances82010.1.7.1 Conventions Used in This Manual82010.1.7.1.1 Acronyms82010.1.7.1.2 Terminology82110.1.7.1.3 Formulae and Nomenclature82210.1.7.2 Compliances82210.2 Cryptography Registers82210.2.1 CRYPTO Registers82310.2.1.1 DMACH0CTL Register (Offset = 0h) [reset = X]82410.2.1.2 DMACH0EXTADDR Register (Offset = 4h) [reset = X]82510.2.1.3 DMACH0LEN Register (Offset = Ch) [reset = X]82610.2.1.4 DMASTAT Register (Offset = 18h) [reset = X]82710.2.1.5 DMASWRESET Register (Offset = 1Ch) [reset = X]82810.2.1.6 DMACH1CTL Register (Offset = 20h) [reset = X]82910.2.1.7 DMACH1EXTADDR Register (Offset = 24h) [reset = X]83010.2.1.8 DMACH1LEN Register (Offset = 2Ch) [reset = X]83110.2.1.9 DMABUSCFG Register (Offset = 78h) [reset = X]83210.2.1.10 DMAPORTERR Register (Offset = 7Ch) [reset = X]83310.2.1.11 DMAHWVER Register (Offset = FCh) [reset = X]83410.2.1.12 KEYWRITEAREA Register (Offset = 400h) [reset = X]83510.2.1.13 KEYWRITTENAREA Register (Offset = 404h) [reset = X]83710.2.1.14 KEYSIZE Register (Offset = 408h) [reset = X]83910.2.1.15 KEYREADAREA Register (Offset = 40Ch) [reset = X]84010.2.1.16 AESKEY2_0 to AESKEY2_3 Register (Offset = 500h to 50Ch) [reset = X]84110.2.1.17 AESKEY3_0 to AESKEY3_3 Register (Offset = 510h to 51Ch) [reset = X]84210.2.1.18 AESIV_0 to AESIV_3 Register (Offset = 540h to 54Ch) [reset = X]84310.2.1.19 AESCTL Register (Offset = 550h) [reset = X]84410.2.1.20 AESDATALEN0 Register (Offset = 554h) [reset = X]84610.2.1.21 AESDATALEN1 Register (Offset = 558h) [reset = X]84710.2.1.22 AESAUTHLEN Register (Offset = 55Ch) [reset = X]84810.2.1.23 AESDATAOUT0 Register (Offset = 560h) [reset = X]84910.2.1.24 AESDATAIN0 Register (Offset = 560h) [reset = X]85010.2.1.25 AESDATAOUT1 Register (Offset = 564h) [reset = X]85110.2.1.26 AESDATAIN1 Register (Offset = 564h) [reset = X]85210.2.1.27 AESDATAOUT2 Register (Offset = 568h) [reset = X]85310.2.1.28 AESDATAIN2 Register (Offset = 568h) [reset = X]85410.2.1.29 AESDATAOUT3 Register (Offset = 56Ch) [reset = X]85510.2.1.30 AESDATAIN3 Register (Offset = 56Ch) [reset = X]85610.2.1.31 AESTAGOUT_0 to AESTAGOUT_3 Register (Offset = 570h to 57Ch) [reset = X]85710.2.1.32 ALGSEL Register (Offset = 700h) [reset = X]85810.2.1.33 DMAPROTCTL Register (Offset = 704h) [reset = X]85910.2.1.34 SWRESET Register (Offset = 740h) [reset = X]86010.2.1.35 IRQTYPE Register (Offset = 780h) [reset = X]86110.2.1.36 IRQEN Register (Offset = 784h) [reset = X]86210.2.1.37 IRQCLR Register (Offset = 788h) [reset = X]86310.2.1.38 IRQSET Register (Offset = 78Ch) [reset = X]86410.2.1.39 IRQSTAT Register (Offset = 790h) [reset = X]86510.2.1.40 HWVER Register (Offset = 7FCh) [reset = 91118778h]86611 I/O Control86711.1 Introduction86811.2 IOC Overview86811.3 I/O Mapping and Configuration86911.3.1 Basic I/O Mapping86911.3.2 MAP AUXIO from the Sensor Controller to DIO Pin86911.3.2.1 Control External LNA/PA (Range Extender) With I/Os86911.3.3 Map 32-kHz System Clock (LF Clock) to DIO/PIN87011.4 Edge Detection on Pin (DIO)87011.4.1 Configure DIO as GPIO Input to Generate Interrupt on EDGE DETECT87011.5 AON IOC State Latching When Powering Off the MCU Domain87011.6 Unused I/O Pins87111.7 GPIO87111.8 I/O Pin Mapping87211.9 Peripheral PORTIDs87311.10 I/O Pin87311.10.1 Physical Pin87311.10.2 Pin Configuration87411.11 I/O Control Registers87511.11.1 AON_IOC Registers87611.11.1.1 IOSTRMIN Register (Offset = 0h) [reset = X]87711.11.1.2 IOSTRMED Register (Offset = 4h) [reset = X]87811.11.1.3 IOSTRMAX Register (Offset = 8h) [reset = X]87911.11.1.4 IOCLATCH Register (Offset = Ch) [reset = X]88011.11.1.5 CLK32KCTL Register (Offset = 10h) [reset = X]88111.11.2 IOC Registers88311.11.2.1 IOCFG0 Register (Offset = 0h) [reset = X]88411.11.2.2 IOCFG1 Register (Offset = 4h) [reset = X]88811.11.2.3 IOCFG2 Register (Offset = 8h) [reset = X]89211.11.2.4 IOCFG3 Register (Offset = Ch) [reset = X]89611.11.2.5 IOCFG4 Register (Offset = 10h) [reset = X]90011.11.2.6 IOCFG5 Register (Offset = 14h) [reset = X]90411.11.2.7 IOCFG6 Register (Offset = 18h) [reset = X]90811.11.2.8 IOCFG7 Register (Offset = 1Ch) [reset = X]91211.11.2.9 IOCFG8 Register (Offset = 20h) [reset = X]91611.11.2.10 IOCFG9 Register (Offset = 24h) [reset = X]92011.11.2.11 IOCFG10 Register (Offset = 28h) [reset = X]92411.11.2.12 IOCFG11 Register (Offset = 2Ch) [reset = X]92811.11.2.13 IOCFG12 Register (Offset = 30h) [reset = X]93211.11.2.14 IOCFG13 Register (Offset = 34h) [reset = X]93611.11.2.15 IOCFG14 Register (Offset = 38h) [reset = X]94011.11.2.16 IOCFG15 Register (Offset = 3Ch) [reset = X]94411.11.2.17 IOCFG16 Register (Offset = 40h) [reset = X]94811.11.2.18 IOCFG17 Register (Offset = 44h) [reset = X]95211.11.2.19 IOCFG18 Register (Offset = 48h) [reset = X]95611.11.2.20 IOCFG19 Register (Offset = 4Ch) [reset = X]96011.11.2.21 IOCFG20 Register (Offset = 50h) [reset = X]96411.11.2.22 IOCFG21 Register (Offset = 54h) [reset = X]96811.11.2.23 IOCFG22 Register (Offset = 58h) [reset = X]97211.11.2.24 IOCFG23 Register (Offset = 5Ch) [reset = X]97611.11.2.25 IOCFG24 Register (Offset = 60h) [reset = X]98011.11.2.26 IOCFG25 Register (Offset = 64h) [reset = X]98411.11.2.27 IOCFG26 Register (Offset = 68h) [reset = X]98811.11.2.28 IOCFG27 Register (Offset = 6Ch) [reset = X]99211.11.2.29 IOCFG28 Register (Offset = 70h) [reset = X]99611.11.2.30 IOCFG29 Register (Offset = 74h) [reset = X]100011.11.2.31 IOCFG30 Register (Offset = 78h) [reset = X]100411.11.2.32 IOCFG31 Register (Offset = 7Ch) [reset = X]100811.11.3 GPIO Registers101211.11.3.1 DOUT3_0 Register (Offset = 0h) [reset = X]101311.11.3.2 DOUT7_4 Register (Offset = 4h) [reset = X]101411.11.3.3 DOUT11_8 Register (Offset = 8h) [reset = X]101511.11.3.4 DOUT15_12 Register (Offset = Ch) [reset = X]101611.11.3.5 DOUT19_16 Register (Offset = 10h) [reset = X]101711.11.3.6 DOUT23_20 Register (Offset = 14h) [reset = X]101811.11.3.7 DOUT27_24 Register (Offset = 18h) [reset = X]101911.11.3.8 DOUT31_28 Register (Offset = 1Ch) [reset = X]102011.11.3.9 DOUT31_0 Register (Offset = 80h) [reset = X]102111.11.3.10 DOUTSET31_0 Register (Offset = 90h) [reset = X]102311.11.3.11 DOUTCLR31_0 Register (Offset = A0h) [reset = X]102511.11.3.12 DOUTTGL31_0 Register (Offset = B0h) [reset = X]102711.11.3.13 DIN31_0 Register (Offset = C0h) [reset = X]102911.11.3.14 DOE31_0 Register (Offset = D0h) [reset = X]103111.11.3.15 EVFLAGS31_0 Register (Offset = E0h) [reset = X]103312 Micro Direct Memory Access (µDMA)103512.1 μDMA Introduction103612.2 Block Diagram103612.3 Functional Description103712.3.1 Channel Assignments103712.3.2 Priority103912.3.3 Arbitration Size103912.3.4 Request Types103912.3.4.1 Single Request104012.3.4.2 Burst Request104012.3.5 Channel Configuration104012.3.6 Transfer Modes104112.3.6.1 Stop Mode104112.3.6.2 Basic Mode104112.3.6.3 Auto Mode104212.3.6.4 Ping-Pong104212.3.6.5 Memory Scatter-Gather Mode104312.3.6.6 Peripheral Scatter-Gather Mode104712.3.7 Transfer Size and Increments105012.3.8 Peripheral Interface105012.3.9 Software Request105012.3.10 Interrupts and Errors105112.4 Initialization and Configuration105112.4.1 Module Initialization105112.4.2 Configuring a Memory-to-Memory Transfer105212.4.2.1 Configure the Channel Attributes105212.4.2.2 Configure the Channel Control Structure105212.4.2.3 Start the Transfer105212.4.3 Configuring Channel Assignments105212.5 µDMA Registers105212.5.1 UDMA Registers105312.5.1.1 STATUS Register (Offset = 0h) [reset = X]105412.5.1.2 CFG Register (Offset = 4h) [reset = X]105512.5.1.3 CTRL Register (Offset = 8h) [reset = X]105612.5.1.4 ALTCTRL Register (Offset = Ch) [reset = 200h]105712.5.1.5 WAITONREQ Register (Offset = 10h) [reset = FFFF1EFFh]105812.5.1.6 SOFTREQ Register (Offset = 14h) [reset = X]105912.5.1.7 SETBURST Register (Offset = 18h) [reset = X]106012.5.1.8 CLEARBURST Register (Offset = 1Ch) [reset = X]106112.5.1.9 SETREQMASK Register (Offset = 20h) [reset = X]106212.5.1.10 CLEARREQMASK Register (Offset = 24h) [reset = X]106312.5.1.11 SETCHANNELEN Register (Offset = 28h) [reset = X]106412.5.1.12 CLEARCHANNELEN Register (Offset = 2Ch) [reset = X]106512.5.1.13 SETCHNLPRIALT Register (Offset = 30h) [reset = X]106612.5.1.14 CLEARCHNLPRIALT Register (Offset = 34h) [reset = X]106712.5.1.15 SETCHNLPRIORITY Register (Offset = 38h) [reset = X]106812.5.1.16 CLEARCHNLPRIORITY Register (Offset = 3Ch) [reset = X]106912.5.1.17 ERROR Register (Offset = 4Ch) [reset = X]107012.5.1.18 REQDONE Register (Offset = 504h) [reset = X]107112.5.1.19 DONEMASK Register (Offset = 520h) [reset = X]107213 Timers107313.1 General-Purpose Timers107413.2 Block Diagram107413.3 Functional Description107513.3.1 GPTM Reset Conditions107613.3.2 Timer Modes107613.3.2.1 One-Shot or Periodic Timer Mode107713.3.2.2 Input Edge-Count Mode107813.3.2.3 Input Edge-Time Mode107913.3.2.4 PWM Mode108013.3.3 Wait-for-Trigger Mode108313.3.4 Synchronizing GP Timer Blocks108313.3.5 Accessing Concatenated 16- and 32-Bit GPTM Register Values108413.4 Initialization and Configuration108413.4.1 One-Shot and Periodic Timer Modes108413.4.2 Input Edge-Count Mode108513.4.3 Input Edge-Timing Mode108513.4.4 PWM Mode108613.4.5 Producing DMA Trigger108613.5 General-Purpose Timer Registers108613.5.1 GPT Registers108713.5.1.1 CFG Register (Offset = 0h) [reset = X]108813.5.1.2 TAMR Register (Offset = 4h) [reset = X]108913.5.1.3 TBMR Register (Offset = 8h) [reset = X]109113.5.1.4 CTL Register (Offset = Ch) [reset = X]109313.5.1.5 SYNC Register (Offset = 10h) [reset = X]109513.5.1.6 IMR Register (Offset = 18h) [reset = X]109613.5.1.7 RIS Register (Offset = 1Ch) [reset = X]109813.5.1.8 MIS Register (Offset = 20h) [reset = X]110013.5.1.9 ICLR Register (Offset = 24h) [reset = X]110213.5.1.10 TAILR Register (Offset = 28h) [reset = FFFFFFFFh]110313.5.1.11 TBILR Register (Offset = 2Ch) [reset = FFFFh]110413.5.1.12 TAMATCHR Register (Offset = 30h) [reset = FFFFFFFFh]110513.5.1.13 TBMATCHR Register (Offset = 34h) [reset = FFFFh]110613.5.1.14 TAPR Register (Offset = 38h) [reset = X]110713.5.1.15 TBPR Register (Offset = 3Ch) [reset = X]110813.5.1.16 TAPMR Register (Offset = 40h) [reset = X]110913.5.1.17 TBPMR Register (Offset = 44h) [reset = X]111013.5.1.18 TAR Register (Offset = 48h) [reset = FFFFFFFFh]111113.5.1.19 TBR Register (Offset = 4Ch) [reset = FFFFh]111213.5.1.20 TAV Register (Offset = 50h) [reset = FFFFFFFFh]111313.5.1.21 TBV Register (Offset = 54h) [reset = FFFFh]111413.5.1.22 RTCPD Register (Offset = 58h) [reset = X]111513.5.1.23 TAPS Register (Offset = 5Ch) [reset = X]111613.5.1.24 TBPS Register (Offset = 60h) [reset = X]111713.5.1.25 TAPV Register (Offset = 64h) [reset = X]111813.5.1.26 TBPV Register (Offset = 68h) [reset = X]111913.5.1.27 DMAEV Register (Offset = 6Ch) [reset = X]112013.5.1.28 ADCEV Register (Offset = 70h) [reset = X]112113.5.1.29 VERSION Register (Offset = FB0h) [reset = 400h]112213.5.1.30 ANDCCP Register (Offset = FB4h) [reset = X]112314 Real-Time Clock112414.1 Introduction112514.2 Functional Specifications112514.2.1 Functional Overview112514.2.2 Free-Running Counter112514.2.3 Channels112514.2.4 Events112614.3 RTC Registers112614.3.1 Register Access112614.3.2 Entering and Wakeup From Sleep112714.3.3 [AON_RTC:SYNC] Register112714.4 Real-Time Clock Registers112714.4.1 AON_RTC Registers112814.4.1.1 CTL Register (Offset = 0h) [reset = X]112914.4.1.2 EVFLAGS Register (Offset = 4h) [reset = X]113114.4.1.3 SEC Register (Offset = 8h) [reset = X]113214.4.1.4 SUBSEC Register (Offset = Ch) [reset = X]113314.4.1.5 SUBSECINC Register (Offset = 10h) [reset = X]113414.4.1.6 CHCTL Register (Offset = 14h) [reset = X]113514.4.1.7 CH0CMP Register (Offset = 18h) [reset = X]113614.4.1.8 CH1CMP Register (Offset = 1Ch) [reset = X]113714.4.1.9 CH2CMP Register (Offset = 20h) [reset = X]113814.4.1.10 CH2CMPINC Register (Offset = 24h) [reset = X]113914.4.1.11 CH1CAPT Register (Offset = 28h) [reset = X]114014.4.1.12 SYNC Register (Offset = 2Ch) [reset = X]114115 Watchdog Timer114215.1 WDT Introduction114315.2 WDT Functional Description114315.3 WDT Initialization and Configuration114415.4 Watchdog Timer Registers114415.4.1 WDT Registers114515.4.1.1 LOAD Register (Offset = 0h) [reset = FFFFFFFFh]114615.4.1.2 VALUE Register (Offset = 4h) [reset = FFFFFFFFh]114715.4.1.3 CTL Register (Offset = 8h) [reset = X]114815.4.1.4 ICR Register (Offset = Ch) [reset = X]114915.4.1.5 RIS Register (Offset = 10h) [reset = X]115015.4.1.6 MIS Register (Offset = 14h) [reset = X]115115.4.1.7 TEST Register (Offset = 418h) [reset = X]115215.4.1.8 INT_CAUS Register (Offset = 41Ch) [reset = X]115315.4.1.9 LOCK Register (Offset = C00h) [reset = X]115416 Random Number Generator115516.1 Overview115616.2 Block Diagram115616.3 TRNG Software Reset115716.4 Interrupt Requests115716.5 TRNG Operation Description115816.5.1 TRNG Shutdown115816.5.2 TRNG Alarms115916.5.3 TRNG Entropy115916.6 TRNG Low-level Programing Guide116016.6.1 Initialization116016.6.1.1 Interfacing Modules116016.6.1.2 TRNG Main Sequence116016.6.1.3 TRNG Operating Modes116116.6.1.3.1 Polling Mode116116.6.1.3.2 Interrupt Mode116216.7 Random Number Generator116216.7.1 TRNG Registers116316.7.1.1 OUT0 Register (Offset = 0h) [reset = X]116416.7.1.2 OUT1 Register (Offset = 4h) [reset = X]116516.7.1.3 IRQFLAGSTAT Register (Offset = 8h) [reset = X]116616.7.1.4 IRQFLAGMASK Register (Offset = Ch) [reset = X]116716.7.1.5 IRQFLAGCLR Register (Offset = 10h) [reset = X]116816.7.1.6 CTL Register (Offset = 14h) [reset = X]116916.7.1.7 CFG0 Register (Offset = 18h) [reset = X]117016.7.1.8 ALARMCNT Register (Offset = 1Ch) [reset = X]117116.7.1.9 FROEN Register (Offset = 20h) [reset = X]117216.7.1.10 FRODETUNE Register (Offset = 24h) [reset = X]117316.7.1.11 ALARMMASK Register (Offset = 28h) [reset = X]117416.7.1.12 ALARMSTOP Register (Offset = 2Ch) [reset = X]117516.7.1.13 LFSR0 Register (Offset = 30h) [reset = X]117616.7.1.14 LFSR1 Register (Offset = 34h) [reset = X]117716.7.1.15 LFSR2 Register (Offset = 38h) [reset = X]117816.7.1.16 HWOPT Register (Offset = 78h) [reset = X]117916.7.1.17 HWVER0 Register (Offset = 7Ch) [reset = X]118016.7.1.18 IRQSTATMASK Register (Offset = 1FD8h) [reset = X]118116.7.1.19 HWVER1 Register (Offset = 1FE0h) [reset = X]118216.7.1.20 IRQSET Register (Offset = 1FECh) [reset = X]118316.7.1.21 SWRESET Register (Offset = 1FF0h) [reset = X]118416.7.1.22 IRQSTAT Register (Offset = 1FF8h) [reset = X]118517 AUX – Sensor Controller with Digital and Analog Peripherals118617.1 Introduction118717.1.1 AUX Hardware Overview118817.2 Memory Mapping118917.2.1 Alias of Commonly Used Registers118917.3 IO Mapping119117.4 Modules119117.4.1 Sensor Controller119117.4.1.1 Introduction119117.4.1.2 Registers119217.4.1.3 Interfaces119217.4.1.4 Events, Sleep, and Clock Management119217.4.1.4.1 WEV1, WEV0 , and SLEEP Instructions119217.4.1.5 Instruction Set119317.4.1.5.1 Memory Access119317.4.1.5.2 I/O Access119317.4.1.5.3 I/O Bit Access119417.4.1.5.4 Arithmetic and Logical Operations119417.4.1.5.5 Shift Operations119517.4.1.5.6 Flow Control119617.4.1.5.7 Events, Sleep, and Power Management119717.4.1.5.8 Miscellaneous Instructions119817.4.1.5.9 Reset119917.4.1.5.10 Limitations119917.4.1.6 Sensor Controller Control and Status119917.4.1.6.1 Single-Stepping and Debugging the Sensor Controller119917.4.1.7 Running a Program120017.4.1.7.1 Use Case – Periodic Wake Up120017.4.2 GPIO Control120017.4.2.1 Event Control120017.4.2.1.1 Software-Defined Events120117.4.2.1.2 Sensor Controller Events120117.4.2.1.3 Events to AON Event Fabric120117.4.2.1.4 Events to MCU120217.4.3 AUX Timers120317.4.4 Time-to-Digital Converter120317.4.4.1 Configuration120317.4.4.2 Clocks120317.4.4.2.1 Start and Stop Source120317.4.4.2.2 Saturation120417.4.4.2.3 Prescaler120417.4.4.3 Performing a Measurement120417.4.5 Semaphores120417.4.6 Oscillator Configuration Interface (DDI)120417.4.7 Analog Configuration Interface (ADI)120417.4.8 Analog MUX120517.4.9 ADC120517.4.9.1 Introduction120517.4.9.2 ADC Reference120517.4.9.3 Configuration120617.4.9.3.1 Sample Mode and Sample Duration120617.4.9.3.2 Input Signal Scaling120617.4.9.3.3 ADC Enable120617.4.9.3.4 Digital Core120617.4.9.3.5 ADC Core Clock120617.4.9.4 Sampling120617.4.9.5 FIFO120717.4.9.6 Interrupts and Events120717.4.9.7 DMA Usage120717.4.9.8 Usage Example – Single Shot ADC Measurement120717.4.9.8.1 Enable Interface Clocks and ADC Clocks120717.4.9.8.2 Configure the ADC Registers120717.4.9.8.3 Sampling120817.4.10 Comparators120817.4.11 Current source120817.5 Power Management120817.5.1 Startup120817.5.2 Power Mode Management120817.5.2.1 Active Mode120817.5.2.2 Power Down120917.5.2.3 Power Off120917.5.3 Wakeup Events120917.5.4 MCU Bus Connection121017.6 Clock Management121017.6.1 System Clocks121017.6.1.1 Active Mode121017.6.1.2 Power Down121117.6.2 Sensor Controller Clock121117.6.3 Peripheral Clocks121117.7 Use Cases121117.7.1 RTC Calibration121117.7.2 Capacitive Sensing121117.7.3 Pulse Counting121117.8 AUX – Sensor Controller Registers121117.8.1 AUX_AIODIO Registers121217.8.1.1 GPIODOUT Register (Offset = 0h) [reset = X]121317.8.1.2 IOMODE Register (Offset = 4h) [reset = X]121417.8.1.3 GPIODIN Register (Offset = 8h) [reset = X]121617.8.1.4 GPIODOUTSET Register (Offset = Ch) [reset = X]121717.8.1.5 GPIODOUTCLR Register (Offset = 10h) [reset = X]121817.8.1.6 GPIODOUTTGL Register (Offset = 14h) [reset = X]121917.8.1.7 GPIODIE Register (Offset = 18h) [reset = X]122017.8.2 AUX_TDC Registers122117.8.2.1 CTL Register (Offset = 0h) [reset = X]122217.8.2.2 STAT Register (Offset = 4h) [reset = X]122317.8.2.3 RESULT Register (Offset = 8h) [reset = X]122417.8.2.4 SATCFG Register (Offset = Ch) [reset = X]122517.8.2.5 TRIGSRC Register (Offset = 10h) [reset = X]122617.8.2.6 TRIGCNT Register (Offset = 14h) [reset = X]122917.8.2.7 TRIGCNTLOAD Register (Offset = 18h) [reset = X]123017.8.2.8 TRIGCNTCFG Register (Offset = 1Ch) [reset = X]123117.8.2.9 PRECTL Register (Offset = 20h) [reset = X]123217.8.2.10 PRECNT Register (Offset = 24h) [reset = X]123417.8.3 AUX_EVCTL Registers123517.8.3.1 VECCFG0 Register (Offset = 0h) [reset = X]123617.8.3.2 VECCFG1 Register (Offset = 4h) [reset = X]123917.8.3.3 SCEWEVSEL Register (Offset = 8h) [reset = X]124217.8.3.4 EVTOAONFLAGS Register (Offset = Ch) [reset = X]124317.8.3.5 EVTOAONPOL Register (Offset = 10h) [reset = X]124417.8.3.6 DMACTL Register (Offset = 14h) [reset = X]124517.8.3.7 SWEVSET Register (Offset = 18h) [reset = X]124617.8.3.8 EVSTAT0 Register (Offset = 1Ch) [reset = X]124717.8.3.9 EVSTAT1 Register (Offset = 20h) [reset = X]124817.8.3.10 EVTOMCUPOL Register (Offset = 24h) [reset = X]124917.8.3.11 EVTOMCUFLAGS Register (Offset = 28h) [reset = X]125117.8.3.12 COMBEVTOMCUMASK Register (Offset = 2Ch) [reset = X]125217.8.3.13 VECFLAGS Register (Offset = 34h) [reset = X]125317.8.3.14 EVTOMCUFLAGSCLR Register (Offset = 38h) [reset = X]125417.8.3.15 EVTOAONFLAGSCLR Register (Offset = 3Ch) [reset = X]125517.8.3.16 VECFLAGSCLR Register (Offset = 40h) [reset = X]125617.8.4 AON_WUC Registers125717.8.4.1 MCUCLK Register (Offset = 0h) [reset = X]125817.8.4.2 AUXCLK Register (Offset = 4h) [reset = X]125917.8.4.3 MCUCFG Register (Offset = 8h) [reset = X]126017.8.4.4 AUXCFG Register (Offset = Ch) [reset = X]126117.8.4.5 AUXCTL Register (Offset = 10h) [reset = X]126217.8.4.6 PWRSTAT Register (Offset = 14h) [reset = X]126317.8.4.7 SHUTDOWN Register (Offset = 18h) [reset = X]126417.8.4.8 CTL0 Register (Offset = 20h) [reset = X]126517.8.4.9 CTL1 Register (Offset = 24h) [reset = X]126617.8.4.10 RECHARGECFG Register (Offset = 30h) [reset = X]126717.8.4.11 RECHARGESTAT Register (Offset = 34h) [reset = X]126917.8.4.12 OSCCFG Register (Offset = 38h) [reset = X]127017.8.4.13 JTAGCFG Register (Offset = 40h) [reset = X]127117.8.4.14 JTAGUSERCODE Register (Offset = 44h) [reset = B99A02Fh]127217.8.5 AUX_TIMER Registers127317.8.5.1 T0CFG Register (Offset = 0h) [reset = X]127417.8.5.2 T1CFG Register (Offset = 4h) [reset = X]127617.8.5.3 T0CTL Register (Offset = 8h) [reset = X]127817.8.5.4 T0TARGET Register (Offset = Ch) [reset = X]127917.8.5.5 T1TARGET Register (Offset = 10h) [reset = X]128017.8.5.6 T1CTL Register (Offset = 14h) [reset = X]128117.8.6 AUX_SMPH Registers128217.8.6.1 SMPH0 Register (Offset = 0h) [reset = X]128317.8.6.2 SMPH1 Register (Offset = 4h) [reset = X]128417.8.6.3 SMPH2 Register (Offset = 8h) [reset = X]128517.8.6.4 SMPH3 Register (Offset = Ch) [reset = X]128617.8.6.5 SMPH4 Register (Offset = 10h) [reset = X]128717.8.6.6 SMPH5 Register (Offset = 14h) [reset = X]128817.8.6.7 SMPH6 Register (Offset = 18h) [reset = X]128917.8.6.8 SMPH7 Register (Offset = 1Ch) [reset = X]129017.8.6.9 AUTOTAKE Register (Offset = 20h) [reset = X]129117.8.7 AUX_ANAIF Registers129217.8.7.1 ADCCTL Register (Offset = 10h) [reset = X]129317.8.7.2 ADCFIFOSTAT Register (Offset = 14h) [reset = X]129517.8.7.3 ADCFIFO Register (Offset = 18h) [reset = X]129617.8.7.4 ADCTRIG Register (Offset = 1Ch) [reset = X]129717.8.7.5 ISRCCTL Register (Offset = 20h) [reset = X]129817.8.8 ADI_4_AUX Registers129917.8.8.1 MUX0 Register (Offset = 0h) [reset = X]130017.8.8.2 MUX1 Register (Offset = 1h) [reset = X]130117.8.8.3 MUX2 Register (Offset = 2h) [reset = X]130217.8.8.4 MUX3 Register (Offset = 3h) [reset = X]130317.8.8.5 ISRC Register (Offset = 4h) [reset = X]130417.8.8.6 COMP Register (Offset = 5h) [reset = X]130517.8.8.7 MUX4 Register (Offset = 7h) [reset = X]130617.8.8.8 ADC0 Register (Offset = 8h) [reset = X]130717.8.8.9 ADC1 Register (Offset = 9h) [reset = X]130817.8.8.10 ADCREF0 Register (Offset = Ah) [reset = X]130917.8.8.11 ADCREF1 Register (Offset = Bh) [reset = X]131018 Battery Monitor and Temperature Sensor131118.1 Introduction131218.2 Functional Description131218.3 BATMON Registers131218.3.1 AON_BATMON Registers131318.3.1.1 CTL Register (Offset = 0h) [reset = X]131418.3.1.2 MEASCFG Register (Offset = 4h) [reset = X]131518.3.1.3 TEMPP0 Register (Offset = Ch) [reset = X]131618.3.1.4 TEMPP1 Register (Offset = 10h) [reset = X]131718.3.1.5 TEMPP2 Register (Offset = 14h) [reset = X]131818.3.1.6 BATMONP0 Register (Offset = 18h) [reset = X]131918.3.1.7 BATMONP1 Register (Offset = 1Ch) [reset = X]132018.3.1.8 IOSTRP0 Register (Offset = 20h) [reset = X]132118.3.1.9 FLASHPUMPP0 Register (Offset = 24h) [reset = X]132218.3.1.10 BAT Register (Offset = 28h) [reset = X]132318.3.1.11 BATUPD Register (Offset = 2Ch) [reset = X]132418.3.1.12 TEMP Register (Offset = 30h) [reset = X]132518.3.1.13 TEMPUPD Register (Offset = 34h) [reset = X]132619 Universal Asynchronous Receivers and Transmitters (UARTS)132719.1 Universal Asynchronous Receiver/Transmitter132819.2 Block Diagram132919.3 Signal Description132919.4 Functional DescriptionFunctional Description section132919.4.1 Transmit and Receive Logic133019.4.2 Baud-Rate Generation133019.4.3 Data Transmission133019.4.4 Modem Handshake Support133119.4.4.1 Signaling133119.4.4.2 Flow Control133119.4.4.2.1 Hardware Flow Control (RTS and CTS)133119.4.4.2.2 Software Flow Control (Modem Status Interrupts)133119.4.5 FIFO Operation133219.4.6 Interrupts133219.4.7 Loopback Operation133319.5 Interface to DMA133319.6 Initialization and Configuration133419.7 UARTS Registers133519.7.1 UART Registers133619.7.1.1 DR Register (Offset = 0h) [reset = X]133719.7.1.2 RSR Register (Offset = 4h) [reset = X]133819.7.1.3 ECR Register (Offset = 4h) [reset = X]133919.7.1.4 FR Register (Offset = 18h) [reset = X]134019.7.1.5 IBRD Register (Offset = 24h) [reset = X]134119.7.1.6 FBRD Register (Offset = 28h) [reset = X]134219.7.1.7 LCRH Register (Offset = 2Ch) [reset = X]134319.7.1.8 CTL Register (Offset = 30h) [reset = X]134419.7.1.9 IFLS Register (Offset = 34h) [reset = X]134519.7.1.10 IMSC Register (Offset = 38h) [reset = X]134619.7.1.11 RIS Register (Offset = 3Ch) [reset = X]134819.7.1.12 MIS Register (Offset = 40h) [reset = X]135019.7.1.13 ICR Register (Offset = 44h) [reset = 0h]135119.7.1.14 DMACTL Register (Offset = 48h) [reset = X]135220 Synchronous Serial Interface (SSI)135320.1 Synchronous Serial Interface135420.2 Block Diagram135520.3 Signal Description135620.4 Functional Description135620.4.1 Bit Rate Generation135620.4.2 FIFO Operation135620.4.2.1 Transmit FIFO135620.4.2.2 Receive FIFO135720.4.3 Interrupts135720.4.4 Frame Formats135820.4.4.1 Texas Instruments Synchronous Serial Frame Format135820.4.4.2 Motorola SPI Frame Format135920.4.4.2.1 SPO Clock Polarity Bit135920.4.4.2.2 SPH Phase-Control Bit135920.4.4.3 Motorola SPI Frame Format With SPO = 0 and SPH = 0135920.4.4.4 Motorola SPI Frame Format With SPO = 0 and SPH = 1136020.4.4.5 Motorola SPI Frame Format With SPO = 1 and SPH = 0136120.4.4.6 Motorola SPI Frame Format With SPO = 1 and SPH = 1136120.4.4.7 MICROWIRE Frame Format136220.5 DMA Operation136420.6 Initialization and Configuration136520.7 SSI Registers136620.7.1 SSI Registers136720.7.1.1 CR0 Register (Offset = 0h) [reset = X]136820.7.1.2 CR1 Register (Offset = 4h) [reset = X]136920.7.1.3 DR Register (Offset = 8h) [reset = X]137020.7.1.4 SR Register (Offset = Ch) [reset = X]137120.7.1.5 CPSR Register (Offset = 10h) [reset = X]137220.7.1.6 IMSC Register (Offset = 14h) [reset = X]137320.7.1.7 RIS Register (Offset = 18h) [reset = X]137420.7.1.8 MIS Register (Offset = 1Ch) [reset = X]137520.7.1.9 ICR Register (Offset = 20h) [reset = X]137620.7.1.10 DMACR Register (Offset = 24h) [reset = X]137721 Inter-Integrated Circuit (I2C) Interface137821.1 Inter-Integrated Circuit Interface137921.2 Block Diagram137921.3 Functional Description137921.3.1 I2C Bus Functional Overview138021.3.1.1 Start and Stop Conditions138021.3.1.2 Data Format With 7-Bit Address138121.3.1.3 Data Validity138121.3.1.4 Acknowledge138121.3.1.5 Arbitration138221.3.2 Available Speed Modes138221.3.2.1 Standard and Fast Modes138221.3.3 Interrupts138221.3.3.1 I2C Master Interrupts138321.3.3.2 I2C Slave Interrupts138321.3.4 Loopback Operation138321.3.5 Command Sequence Flow Charts138321.3.5.1 I2C Master Command Sequences138421.3.5.2 I2C Slave Command Sequences139021.4 Initialization and Configuration139121.5 I2C Registers139121.5.1 I2C Registers139221.5.1.1 SOAR Register (Offset = 0h) [reset = X]139321.5.1.2 SSTAT Register (Offset = 4h) [reset = X]139421.5.1.3 SCTL Register (Offset = 4h) [reset = X]139521.5.1.4 SDR Register (Offset = 8h) [reset = X]139621.5.1.5 SIMR Register (Offset = Ch) [reset = X]139721.5.1.6 SRIS Register (Offset = 10h) [reset = X]139821.5.1.7 SMIS Register (Offset = 14h) [reset = X]139921.5.1.8 SICR Register (Offset = 18h) [reset = X]140021.5.1.9 MSA Register (Offset = 800h) [reset = X]140121.5.1.10 MSTAT Register (Offset = 804h) [reset = X]140221.5.1.11 MCTRL Register (Offset = 804h) [reset = X]140321.5.1.12 MDR Register (Offset = 808h) [reset = X]140421.5.1.13 MTPR Register (Offset = 80Ch) [reset = X]140521.5.1.14 MIMR Register (Offset = 810h) [reset = X]140621.5.1.15 MRIS Register (Offset = 814h) [reset = X]140721.5.1.16 MMIS Register (Offset = 818h) [reset = X]140821.5.1.17 MICR Register (Offset = 81Ch) [reset = X]140921.5.1.18 MCR Register (Offset = 820h) [reset = X]141022 Integrated Interchip Sound (I2S) Module141122.1 Introduction141222.2 Digital Audio Interface141222.3 Frame Configuration141322.4 Pin Configuration141322.5 Clock Configuration141322.5.1 WCLK, BCLK, and MCLK Division Ratio141422.6 Serial Interface Formats141422.6.1 I2S141422.6.2 Left Justified (LJF)141522.6.3 Right Justified (RJF)141522.6.4 DSP141622.7 Memory Interface141722.7.1 Word Lengths141722.7.2 Audio Channels141722.7.3 Memory Buffers and Pointers141822.8 Samplestamp Generator141822.8.1 Counters and Registers141922.8.2 Starting Input and Output Pins142022.8.3 Samplestamp Capturing142022.9 Usage142122.9.1 Start-up Sequence142122.9.2 Termination Sequence142222.10 I2S Registers142222.10.1 I2S Registers142322.10.1.1 AIFWCLKSRC Register (Offset = 0h) [reset = X]142422.10.1.2 AIFDMACFG Register (Offset = 4h) [reset = X]142522.10.1.3 AIFDIRCFG Register (Offset = 8h) [reset = X]142622.10.1.4 AIFFMTCFG Register (Offset = Ch) [reset = X]142722.10.1.5 AIFWMASK0 Register (Offset = 10h) [reset = X]142822.10.1.6 AIFWMASK1 Register (Offset = 14h) [reset = X]142922.10.1.7 AIFWMASK2 Register (Offset = 18h) [reset = X]143022.10.1.8 AIFPWMVALUE Register (Offset = 1Ch) [reset = X]143122.10.1.9 AIFINPTRNEXT Register (Offset = 20h) [reset = X]143222.10.1.10 AIFINPTR Register (Offset = 24h) [reset = X]143322.10.1.11 AIFOUTPTRNEXT Register (Offset = 28h) [reset = X]143422.10.1.12 AIFOUTPTR Register (Offset = 2Ch) [reset = X]143522.10.1.13 STMPCTL Register (Offset = 34h) [reset = X]143622.10.1.14 STMPXCNTCAPT0 Register (Offset = 38h) [reset = X]143722.10.1.15 STMPXPER Register (Offset = 3Ch) [reset = X]143822.10.1.16 STMPWCNTCAPT0 Register (Offset = 40h) [reset = X]143922.10.1.17 STMPWPER Register (Offset = 44h) [reset = X]144022.10.1.18 STMPINTRIG Register (Offset = 48h) [reset = X]144122.10.1.19 STMPOUTTRIG Register (Offset = 4Ch) [reset = X]144222.10.1.20 STMPWSET Register (Offset = 50h) [reset = X]144322.10.1.21 STMPWADD Register (Offset = 54h) [reset = X]144422.10.1.22 STMPXPERMIN Register (Offset = 58h) [reset = X]144522.10.1.23 STMPWCNT Register (Offset = 5Ch) [reset = X]144622.10.1.24 STMPXCNT Register (Offset = 60h) [reset = X]144722.10.1.25 STMPXCNTCAPT1 Register (Offset = 64h) [reset = X]144822.10.1.26 STMPWCNTCAPT1 Register (Offset = 68h) [reset = X]144922.10.1.27 IRQMASK Register (Offset = 70h) [reset = X]145022.10.1.28 IRQFLAGS Register (Offset = 74h) [reset = X]145122.10.1.29 IRQSET Register (Offset = 78h) [reset = X]145222.10.1.30 IRQCLR Register (Offset = 7Ch) [reset = X]145323 Radio145423.1 RF Core145523.1.1 High-Level Description and Overview145523.2 Radio Doorbell145623.2.1 Operational Description145723.3 RF Core HAL145723.3.1 Hardware Support145723.3.2 Firmware Support145723.3.2.1 Commands145823.3.2.2 Command Status145923.3.2.3 Interrupts146123.3.2.4 Passing Data146123.3.2.5 Command Scheduling146123.3.2.5.1 Triggers146223.3.2.5.2 Conditional Execution146323.3.2.5.3 Handling Before Start of Command146423.3.2.6 Command Data Structures146423.3.2.6.1 Radio Operation Command Structure146523.3.2.7 Data Entry Structures146523.3.2.7.1 Data Entry Queue146523.3.2.7.2 Data Entry146623.3.2.7.3 Pointer Entry146723.3.2.7.4 RX Multi-Element Entry146723.3.2.8 External Signaling146823.3.3 Command Definitions146823.3.3.1 Protocol-Independent Radio Operation Commands146823.3.3.1.1 CMD_NOP: No Operation Command146923.3.3.1.2 CMD_RADIO_SETUP: Set Up Radio Settings Command146923.3.3.1.3 CMD_FS_POWERUP: Power-Up Frequency Synthesizer147423.3.3.1.4 CMD_FS_POWERDOWN: Power Down Frequency Synthesizer147423.3.3.1.5 CMD_FS: Frequency Synthesizer Controls Command147423.3.3.1.6 CMD_FS_OFF: Turn Off Frequency Synthesizer147523.3.3.1.7 CMD_RX_TEST: Receiver Test Command147523.3.3.1.8 CMD_TX_TEST: Transmitter Test Command147623.3.3.1.9 CMD_SYNC_STOP_RAT: Synchronize and Stop Radio Timer Command147723.3.3.1.10 CMD_SYNC_START_RAT: Synchronously Start Radio Timer Command147723.3.3.1.11 CMD_COUNT: Counter Command147823.3.3.1.12 CMD_SCH_IMM: Run Immediate Command as Radio Operation147823.3.3.1.13 CMD_COUNT_BRANCH: Counter Command With Branch of Command Chain147923.3.3.1.14 CMD_PATTERN_CHECK: Check a Value in Memory Against a Pattern148023.3.4 Protocol-Independent Direct and Immediate Commands148123.3.4.1 CMD_ABORT: Abort Command148123.3.4.2 CMD_STOP: Stop Command148123.3.4.3 CMD_GET_RSSI: Read RSSI Command148223.3.4.4 CMD_UPDATE_RADIO_SETUP: Update Radio Settings Command148223.3.4.5 CMD_TRIGGER: Generate Command Trigger148223.3.4.6 CMD_GET_FW_INFO: Request Information on the Firmware Being Run148323.3.4.7 CMD_START_RAT: Asynchronously Start Radio Timer Command148323.3.4.8 CMD_PING: Respond With Interrupt148323.3.4.9 CMD_SET_RAT_CMP: Set RAT Channel to Compare Mode148323.3.4.10 CMD_SET_RAT_CPT: Set RAT Channel to Capture Mode148423.3.4.11 CMD_DISABLE_RAT_CH: Disable RAT Channel148423.3.4.12 CMD_SET_RAT_OUTPUT: Set RAT Output to a Specified Mode148523.3.4.13 CMD_ARM_RAT_CH: Arm RAT Channel148523.3.4.14 CMD_DISARM_RAT_CH: Disarm RAT Channel148623.3.4.15 CMD_SET_TX_POWER: Set Transmit Power148623.3.4.16 CMD_UPDATE_FS: Set New Synth Frequency Without Recalibration148623.3.4.17 CMD_BUS_REQUEST: Request System BUS Available for RF Core148723.3.5 Immediate Commands for Data Queue Manipulation148723.3.5.1 CMD_ADD_DATA_ENTRY: Add Data Entry to Queue148723.3.5.2 CMD_REMOVE_DATA_ENTRY: Remove First Data Entry From Queue148823.3.5.3 CMD_FLUSH_QUEUE: Flush Queue148823.3.5.4 CMD_CLEAR_RX: Clear All RX Queue Entries148923.3.5.5 CMD_REMOVE_PENDING_ENTRIES: Remove Pending Entries From Queue148923.4 Data Queue Usage149123.4.1 Operations on Data Queues Only Available for Internal Radio CPU Operations149123.4.1.1 PROC_ALLOCATE_TX: Allocate TX Entry for Reading149123.4.1.2 PROC_FREE_DATA_ENTRY: Free Allocated Data Entry149123.4.1.3 PROC_FINISH_DATA_ENTRY: Finish Use of First Data Entry From Queue149123.4.1.4 PROC_ALLOCATE_RX: Allocate RX Buffer for Storing Data149223.4.1.5 PROC_FINISH_RX: Commit Received Data to RX Data Entry149323.4.2 Radio CPU Usage Model149323.4.2.1 Receive Queues149323.4.2.2 Transmit Queues149323.5 IEEE 802.15.4149423.5.1 IEEE 802.15.4 Commands149423.5.1.1 IEEE 802.15.4 Radio Operation Command Structures149423.5.1.2 IEEE 802.15.4 Immediate Command Structures149623.5.1.3 Output Structures149723.5.1.4 Other Structures and Bit Fields149823.5.2 Interrupts150123.5.3 Data Handling150123.5.3.1 Receive Buffers150123.5.3.2 Transmit Buffers150223.5.4 Radio Operation Commands150223.5.4.1 RX Operation150323.5.4.1.1 Frame Filtering and Source Matching150423.5.4.1.2 Frame Reception150523.5.4.1.3 ACK Transmission150623.5.4.1.4 End of Receive Operation150623.5.4.1.5 CCA Monitoring150723.5.4.2 Energy Detect Scan Operation150823.5.4.3 CSMA-CA Operation150823.5.4.4 Transmit Operation151123.5.4.5 Receive Acknowledgment Operation151223.5.4.6 Abort Background-Level Operation Command151323.5.4.7 Update Radio Settings Command151323.5.5 Immediate Commands151423.5.5.1 Modify CCA Parameter Command151423.5.5.2 Modify Frame-Filtering Parameter Command151423.5.5.3 Enable or Disable Source Matching Entry Command151423.5.5.4 Abort Foreground-Level Operation Command151523.5.5.5 Stop Foreground-Level Operation Command151523.5.5.6 Request CCA and RSSI Information Command151523.6 Bluetooth Low Energy151523.6.1 Bluetooth Low Energy Commands151523.6.1.1 Command Data Definitions151623.6.1.1.1 BLE Command Structures151623.6.1.2 Parameter Structures151723.6.1.3 Output Structures152023.6.1.4 Other Structures and Bit Fields152223.6.2 Interrupts152423.6.3 Data Handling152423.6.3.1 Receive Buffers152523.6.3.2 Transmit Buffers152523.6.4 Radio Operation Command Descriptions152523.6.4.1 Link Layer Connection152723.6.4.2 Slave Command153023.6.4.3 Master Command153023.6.4.4 Advertiser153123.6.4.4.1 Connectable Undirected-Advertiser Command153423.6.4.4.2 Connectable Directed-Advertiser Command153423.6.4.4.3 Non-Connectable Advertiser Command153523.6.4.4.4 Scannable Undirected-Advertiser Command153523.6.4.5 Scanner Command153623.6.4.6 Initiator Command154023.6.4.7 Generic Receiver Command154223.6.4.8 PHY Test Transmit Command154423.6.4.9 White List Processing154523.6.5 Immediate Commands154623.6.5.1 Update Advertising Payload Command154623.7 Radio Registers154623.7.1 RFC_DBELL Registers154723.7.1.1 CMDR Register (Offset = 0h) [reset = X]154823.7.1.2 CMDSTA Register (Offset = 4h) [reset = X]154923.7.1.3 RFHWIFG Register (Offset = 8h) [reset = X]155023.7.1.4 RFHWIEN Register (Offset = Ch) [reset = X]155223.7.1.5 RFCPEIFG Register (Offset = 10h) [reset = X]155323.7.1.6 RFCPEIEN Register (Offset = 14h) [reset = FFFFFFFFh]155623.7.1.7 RFCPEISL Register (Offset = 18h) [reset = X]155823.7.1.8 RFACKIFG Register (Offset = 1Ch) [reset = X]156123.7.1.9 SYSGPOCTL Register (Offset = 20h) [reset = X]156223.7.2 RFC_PWR Registers156523.7.2.1 PWMCLKEN Register (Offset = 0h) [reset = X]156623.7.3 RFC_RAT Registers156823.7.3.1 RATCNT Register (Offset = 4h) [reset = X]1569Important Notice1570Größe: 7,05 MBSeiten: 1570Language: EnglishHandbuch öffnen