Texas Instruments CC2650DK Benutzerhandbuch
µDMA Registers
12.5.1.2 CFG Register (Offset = 4h) [reset = X]
CFG is shown in
and described in
.
Configuration
Figure 12-8. CFG Register
31
30
29
28
27
26
25
24
RESERVED
W-X
23
22
21
20
19
18
17
16
RESERVED
W-X
15
14
13
12
11
10
9
8
RESERVED
W-X
7
6
5
4
3
2
1
0
PRTOCTRL
RESERVED
MASTERENAB
LE
W-X
W-X
W-X
Table 12-9. CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
31-8
RESERVED
W
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
7-5
PRTOCTRL
W
X
Sets the AHB-Lite bus protocol protection state by controlling the
AHB signal HProt[3:1] as follows: Bit [7] Controls HProt[3] to indicate
if a cacheable access is occurring. Bit [6] Controls HProt[2] to
indicate if a bufferable access is occurring. Bit [5] Controls HProt[1]
to indicate if a privileged access is occurring. When bit [n] = 1 then
the corresponding HProt is high. When bit [n] = 0 then the
corresponding HProt is low.
AHB signal HProt[3:1] as follows: Bit [7] Controls HProt[3] to indicate
if a cacheable access is occurring. Bit [6] Controls HProt[2] to
indicate if a bufferable access is occurring. Bit [5] Controls HProt[1]
to indicate if a privileged access is occurring. When bit [n] = 1 then
the corresponding HProt is high. When bit [n] = 0 then the
corresponding HProt is low.
4-1
RESERVED
W
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
0
MASTERENABLE
W
X
Enables the controller: 0: Disables the controller 1: Enables the
controller
controller
1055
SWCU117A – February 2015 – Revised March 2015
Micro Direct Memory Access (µDMA)
Copyright © 2015, Texas Instruments Incorporated