Texas Instruments CC2650DK Benutzerhandbuch
General-Purpose Timer Registers
13.5.1 GPT Registers
lists the memory-mapped registers for the GPT. All register offset addresses not listed in
should be considered as reserved locations and the register contents should not be modified.
Table 13-7. GPT Registers
Offset
Acronym
Register Name
Section
0h
CFG
Configuration
4h
TAMR
Timer A Mode
8h
TBMR
Timer B Mode
Ch
CTL
Control
10h
SYNC
Synch Register
18h
IMR
Interrupt Mask
1Ch
RIS
Raw Interrupt Status
20h
MIS
Masked Interrupt Status
24h
ICLR
Interrupt Clear
28h
TAILR
Timer A Interval Load Register
2Ch
TBILR
Timer B Interval Load Register
30h
TAMATCHR
Timer A Match Register
34h
TBMATCHR
Timer B Match Register
38h
TAPR
Timer A Pre-scale
3Ch
TBPR
Timer B Pre-scale
40h
TAPMR
Timer A Pre-scale Match
44h
TBPMR
Timer B Pre-scale Match
48h
TAR
Timer A Register
4Ch
TBR
Timer B Register
50h
TAV
Timer A Value
54h
TBV
Timer B Value
58h
RTCPD
RTC Pre-divide Value
5Ch
TAPS
Timer A Pre-scale Snap-shot
60h
TBPS
Timer A Pre-scale Snap-shot
64h
TAPV
Timer A Pre-scale Value
68h
TBPV
Timer B Pre-scale Value
6Ch
DMAEV
DMA Event
70h
ADCEV
ADC Event
FB0h
VERSION
Peripheral Version
FB4h
ANDCCP
Combined CCP Output
1087
SWCU117A – February 2015 – Revised March 2015
Timers
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