Texas Instruments CC2650DK Benutzerhandbuch
Real-Time Clock Registers
14.4.1.5 SUBSECINC Register (Offset = 10h) [reset = X]
SUBSECINC is shown in
and described in
.
Subseconds Increment Value added to SUBSEC.VALUE on every **SCLK_LF **clock cycle.
Figure 14-6. SUBSECINC Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
VALUEINC
R-X
R-800000h
Table 14-6. SUBSECINC Register Field Descriptions
Bit
Field
Type
Reset
Description
31-24
RESERVED
R
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
23-0
VALUEINC
R
800000h
This value compensates for a SCLK_LF clock which has an offset
from 32768 Hz. The compensation value can be found as 2^38 /
freq, where freq is SCLK_LF clock frequency in Hertz This value is
added to SUBSEC.VALUE on every cycle, and carry of this is added
to SEC.VALUE. To perform the addition, bits [23:6] are aligned with
SUBSEC.VALUE bits [17:0]. The remaining bits [5:0] are
accumulated in a hidden 6-bit register that generates a carry into the
above mentioned addition on overflow. The default value
corresponds to incrementing by precisely 1/32768 of a second.
NOTE: This register is read only. Modification of the register value
must be done using registers AUX_WUC:RTCSUBSECINC1 ,
AUX_WUC:RTCSUBSECINC0 and
AUX_WUC:RTCSUBSECINCCTL
from 32768 Hz. The compensation value can be found as 2^38 /
freq, where freq is SCLK_LF clock frequency in Hertz This value is
added to SUBSEC.VALUE on every cycle, and carry of this is added
to SEC.VALUE. To perform the addition, bits [23:6] are aligned with
SUBSEC.VALUE bits [17:0]. The remaining bits [5:0] are
accumulated in a hidden 6-bit register that generates a carry into the
above mentioned addition on overflow. The default value
corresponds to incrementing by precisely 1/32768 of a second.
NOTE: This register is read only. Modification of the register value
must be done using registers AUX_WUC:RTCSUBSECINC1 ,
AUX_WUC:RTCSUBSECINC0 and
AUX_WUC:RTCSUBSECINCCTL
1134
Real-Time Clock
SWCU117A – February 2015 – Revised March 2015
Copyright © 2015, Texas Instruments Incorporated