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TRNG Software Reset
nondeterministic. Each FRO has an error detection circuit that checks for repeating patterns coming
out of the FRO. If a repeating pattern is detected, the FRO is suspect of having locked onto the
sampling clock, which drastically reduces the amount of entropy generated by that FRO (this is
signaled as a FRO error event).
out of the FRO. If a repeating pattern is detected, the FRO is suspect of having locked onto the
sampling clock, which drastically reduces the amount of entropy generated by that FRO (this is
signaled as a FRO error event).
•
The second part is the entropy accumulation circuit that uses an XOR tree to combine the sampled
FRO clock outputs and an 81-bit LFSR to accumulate entropy ([TRNG:LFSR0], [TRNG:LFSR1], and
[TRNG:LFSR2] registers give the 81 bits main entropy accumulation LFSR).
FRO clock outputs and an 81-bit LFSR to accumulate entropy ([TRNG:LFSR0], [TRNG:LFSR1], and
[TRNG:LFSR2] registers give the 81 bits main entropy accumulation LFSR).
The true entropy source is based upon a predetermined number of free-running oscillators (FROs). The
accumulation of timing jitter, caused (for the largest part) by shot noise, creates uncertainty intervals for
the output transitions of each FRO. Sampling within the uncertainly interval generates a small amount of
entropy, which is accumulated in an LFSR. Entropy generation with multiple FROs in parallel allows the
entropy accumulation to be done far more rapidly than is possible with one FRO.
accumulation of timing jitter, caused (for the largest part) by shot noise, creates uncertainty intervals for
the output transitions of each FRO. Sampling within the uncertainly interval generates a small amount of
entropy, which is accumulated in an LFSR. Entropy generation with multiple FROs in parallel allows the
entropy accumulation to be done far more rapidly than is possible with one FRO.
16.3 TRNG Software Reset
A software reset of the module can be done by writing 1 to [TRNG:SWRESET:RESET]. When a software
reset completes [TRNG:SWRESET:RESET] is automatically reset to 0. By polling
[TRNG:SWRESET:RESET] for 0 the software can ensure that the reset is completed, the software reset
must be completed before doing any TRNG operations.
reset completes [TRNG:SWRESET:RESET] is automatically reset to 0. By polling
[TRNG:SWRESET:RESET] for 0 the software can ensure that the reset is completed, the software reset
must be completed before doing any TRNG operations.
There is also a reset possibility from the PRCM module by writing a 1 to the
[PRCM:RESETSECDMA:TRNG], which is automatically reset. This reset enables the asynchronous reset
input to the module and not the internal reset, thus from a module perspective this is the same as doing
HW reset. SW must ensure that no access is done towards the TRNG while in reset state.
[PRCM:RESETSECDMA:TRNG], which is automatically reset. This reset enables the asynchronous reset
input to the module and not the internal reset, thus from a module perspective this is the same as doing
HW reset. SW must ensure that no access is done towards the TRNG while in reset state.
The software reset will only reset the TRNG core and make sure the Interconnect interface is not
terminated abnormally. The PRCM reset will act as a power-on reset for the module and thus instantly
terminate any transactions and ongoing accumulation, thus care must be taken for using the PRCM reset
source – can safely be combined with a module clock gating prior to reset activation.
terminated abnormally. The PRCM reset will act as a power-on reset for the module and thus instantly
terminate any transactions and ongoing accumulation, thus care must be taken for using the PRCM reset
source – can safely be combined with a module clock gating prior to reset activation.
16.4 Interrupt Requests
An interrupt request, TRNG_IRQ is generated when data is ready for transmission (or an alarm was
triggered).
triggered).
lists the event flags, and their masks, that can cause module interrupts.
Table 16-1. Events
Event Flag
Event Mask
Description
[TRNG:IRQFLAGMASK:RDY]
and
and
Not used, but can be read for combined status of the two
[TRNG:IRQSTAT:STAT]
[TRNG:IRQFLAGMASK:
available interrupts
SHUTDOWN_OVF]
When 1, data is available in the [TRNG:OUT1] and
[TRNG:IRQFLAGSTAT:RDY]
[TRNG:IRQFLAGMASK:RDY]
[TRNG:OUT0] registers. Use [TRNG:IRQFLAGCLR:RDY] to
clear it.
clear it.
When 1, the number of FROs shut down after a second error
event (the number of ‘1’ bits in the [TRNG:ALARMSTOP]
event (the number of ‘1’ bits in the [TRNG:ALARMSTOP]
[TRNG:IRQFLAGSTAT:
[TRNG:IRQFLAGMASK:
register) has exceeded the threshold set by [TRNG:ALARMCNT:
SHUTDOWN_OVF]
SHUTDOWN_OFV]
SHUTDOWN_THR]. Use [TRNG:IRQFLAGCLR:
SHUTDOWN_OVF] to clear it.
SHUTDOWN_OVF] to clear it.
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SWCU117A – February 2015 – Revised March 2015
Random Number Generator
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