Texas Instruments CC2650DK Benutzerhandbuch
AUX – Sensor Controller Registers
17.8.8.8 ADC0 Register (Offset = 8h) [reset = X]
ADC0 is shown in
and described in
.
ADC Control 0
Figure 17-77. ADC0 Register
7
6
5
4
3
2
1
0
SMPL_MODE
SMPL_CYCLE_EXP
RESERVED
RESET_N
EN
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
Table 17-102. ADC0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
SMPL_MODE
R/W
X
ADC Sampling mode: 0: Synchronous mode 1: Asynchronous mode
The ADC does a sample-and-hold before conversion. In
synchronous mode the sampling starts when the ADC clock detects
a rising edge on the trigger signal. Jitter/uncertainty will be inferred in
the detection if the trigger signal originates from a domain that is
asynchronous to the ADC clock. SMPL_CYCLE_EXP determines the
the duration of sampling as 2^(SMPL_CYCLE_EXP+1) * 1/6MHz.
Conversion starts immediately after sampling ends. In asynchronous
mode the sampling is continuous when enabled. Sampling ends and
conversion starts immediately with the rising edge of the trigger
signal. Sampling restarts when the conversion has finished.
Asynchronous mode is useful when it is important to avoid jitter in
the sampling instant of an externally driven signal
The ADC does a sample-and-hold before conversion. In
synchronous mode the sampling starts when the ADC clock detects
a rising edge on the trigger signal. Jitter/uncertainty will be inferred in
the detection if the trigger signal originates from a domain that is
asynchronous to the ADC clock. SMPL_CYCLE_EXP determines the
the duration of sampling as 2^(SMPL_CYCLE_EXP+1) * 1/6MHz.
Conversion starts immediately after sampling ends. In asynchronous
mode the sampling is continuous when enabled. Sampling ends and
conversion starts immediately with the rising edge of the trigger
signal. Sampling restarts when the conversion has finished.
Asynchronous mode is useful when it is important to avoid jitter in
the sampling instant of an externally driven signal
6-3
SMPL_CYCLE_EXP
R/W
X
Controls number of 6 MHz clock cycles in sampling/tracking mode
before conversion. The sampling time will be 2^(SMPL_CYCLE_EXP
+ 1) 6 MHz clock periods. Giving a range of 2 to 65536 clock periods
sampling time (up to 10.9ms). This setting only has effect in
synchronous mode (SMPL_MODE =0). The default minimum value
should be 3 (2.7us sampling time). Less than that should be
considered experimental.
before conversion. The sampling time will be 2^(SMPL_CYCLE_EXP
+ 1) 6 MHz clock periods. Giving a range of 2 to 65536 clock periods
sampling time (up to 10.9ms). This setting only has effect in
synchronous mode (SMPL_MODE =0). The default minimum value
should be 3 (2.7us sampling time). Less than that should be
considered experimental.
2
RESERVED
R/W
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
1
RESET_N
R/W
X
Reset ADC digital subchip, active low. ADC must be reset every time
it is reconfigured. 0: Reset 1: Normal operation
it is reconfigured. 0: Reset 1: Normal operation
0
EN
R/W
X
ADC Enable 0: Disable 1: Enable
1307
SWCU117A – February 2015 – Revised March 2015
AUX – Sensor Controller with Digital and Analog Peripherals
Copyright © 2015, Texas Instruments Incorporated