Texas Instruments CC2650DK Benutzerhandbuch
UARTS Registers
19.7.1.5 IBRD Register (Offset = 24h) [reset = X]
IBRD is shown in
and described in
Integer Baud-Rate Divisor If this register is modified while trasmission or reception is on-going, the
baudrate will not be updated until transmission or reception of the current character is complete.
baudrate will not be updated until transmission or reception of the current character is complete.
Figure 19-8. IBRD Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
DIVINT
R/W-X
R/W-X
Table 19-8. IBRD Register Field Descriptions
Bit
Field
Type
Reset
Description
31-16
RESERVED
R/W
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
15-0
DIVINT
R/W
X
The integer baud rate divisor: The baud rate divisor is calculated
using the formula below: Baud rate divisor = (UART reference clock
frequency) / (16 * Baud rate) Baud rate divisor must be minimum 1
and maximum 65535. That is, DIVINT=0 does not give a valid baud
rate. Similarly, if DIVINT=0xFFFF, any non-zero values in
FBRD.DIVFRAC will be illegal. A valid value must be written to this
field before the UART can be used for RX or TX operations.
using the formula below: Baud rate divisor = (UART reference clock
frequency) / (16 * Baud rate) Baud rate divisor must be minimum 1
and maximum 65535. That is, DIVINT=0 does not give a valid baud
rate. Similarly, if DIVINT=0xFFFF, any non-zero values in
FBRD.DIVFRAC will be illegal. A valid value must be written to this
field before the UART can be used for RX or TX operations.
1341
SWCU117A – February 2015 – Revised March 2015
Universal Asynchronous Receivers and Transmitters (UARTS)
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