Texas Instruments CC2650DK Benutzerhandbuch
SSI Registers
20.7.1.5 CPSR Register (Offset = 10h) [reset = X]
CPSR is shown in
and described in
.
Clock Prescale
Figure 20-17. CPSR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
CPSDVSR
R-X
R/W-X
Table 20-7. CPSR Register Field Descriptions
Bit
Field
Type
Reset
Description
31-8
RESERVED
R
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
7-0
CPSDVSR
R/W
X
Clock prescale divisor: This field specifies the division factor by
which the input system clock to SSI must be internally divided before
further use. The value programmed into this field must be an even
non-zero number (2-254). The least significant bit of the
programmed number is hard-coded to zero. If an odd number is
written to this register, data read back from this register has the least
significant bit as zero.
which the input system clock to SSI must be internally divided before
further use. The value programmed into this field must be an even
non-zero number (2-254). The least significant bit of the
programmed number is hard-coded to zero. If an odd number is
written to this register, data read back from this register has the least
significant bit as zero.
1372
Synchronous Serial Interface (SSI)
SWCU117A – February 2015 – Revised March 2015
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