Texas Instruments CC2650DK Benutzerhandbuch
I
2
C Registers
21.5.1.7 SMIS Register (Offset = 14h) [reset = X]
SMIS is shown in
and described in
Slave Masked Interrupt Status This register show which interrupt is active (based on result from SRIS and
SIMR).
SIMR).
Figure 21-20. SMIS Register
31
30
29
28
27
26
25
24
RESERVED
R-X
23
22
21
20
19
18
17
16
RESERVED
R-X
15
14
13
12
11
10
9
8
RESERVED
R-X
7
6
5
4
3
2
1
0
RESERVED
STOPMIS
STARTMIS
DATAMIS
R-X
R-X
R-X
R-X
Table 21-9. SMIS Register Field Descriptions
Bit
Field
Type
Reset
Description
31-3
RESERVED
R
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
2
STOPMIS
R
X
Stop condition masked interrupt status 0: An interrupt has not
occurred or is masked/disabled. 1: An unmasked Stop condition
interrupt is pending. This bit is cleared by writing a 1 to the
SICR.STOPIC.
occurred or is masked/disabled. 1: An unmasked Stop condition
interrupt is pending. This bit is cleared by writing a 1 to the
SICR.STOPIC.
1
STARTMIS
R
X
Start condition masked interrupt status 0: An interrupt has not
occurred or is masked/disabled. 1: An unmasked Start condition
interrupt is pending. This bit is cleared by writing a 1 to the
SICR.STARTIC.
occurred or is masked/disabled. 1: An unmasked Start condition
interrupt is pending. This bit is cleared by writing a 1 to the
SICR.STARTIC.
0
DATAMIS
R
X
Data masked interrupt status 0: An interrupt has not occurred or is
masked/disabled. 1: An unmasked data received or data requested
interrupt is pending. This bit is cleared by writing a 1 to the
SICR.DATAIC.
masked/disabled. 1: An unmasked data received or data requested
interrupt is pending. This bit is cleared by writing a 1 to the
SICR.DATAIC.
1399
SWCU117A – February 2015 – Revised March 2015
Inter-Integrated Circuit (I
2
C) Interface
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