Texas Instruments CC2650DK Benutzerhandbuch
I
2
C Registers
21.5.1.11 MCTRL Register (Offset = 804h) [reset = X]
MCTRL is shown in
and described in
Master Control This register accesses status bits when read and control bits when written. When read, the
status register indicates the state of the I2C bus controller as stated in MSTAT. When written, the control
register configures the I2C controller operation. To generate a single transmit cycle, the I2C Master Slave
Address (MSA) register is written with the desired address, the MSA.RS bit is cleared, and this register is
written with * ACK=X (0 or 1), * STOP=1, * START=1, * RUN=1 to perform the operation and stop. When
the operation is completed (or aborted due an error), an interrupt becomes active and the data may be
read from the MDR register.
status register indicates the state of the I2C bus controller as stated in MSTAT. When written, the control
register configures the I2C controller operation. To generate a single transmit cycle, the I2C Master Slave
Address (MSA) register is written with the desired address, the MSA.RS bit is cleared, and this register is
written with * ACK=X (0 or 1), * STOP=1, * START=1, * RUN=1 to perform the operation and stop. When
the operation is completed (or aborted due an error), an interrupt becomes active and the data may be
read from the MDR register.
Figure 21-24. MCTRL Register
31
30
29
28
27
26
25
24
RESERVED
W-X
23
22
21
20
19
18
17
16
RESERVED
W-X
15
14
13
12
11
10
9
8
RESERVED
W-X
7
6
5
4
3
2
1
0
RESERVED
ACK
STOP
START
RUN
W-X
W-X
W-X
W-X
W-X
Table 21-13. MCTRL Register Field Descriptions
Bit
Field
Type
Reset
Description
31-4
RESERVED
W
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
3
ACK
W
X
Data acknowledge enable 0: The received data byte is not
acknowledged automatically by the master. 1: The received data
byte is acknowledged automatically by the master. This bit-field must
be cleared when the I2C bus controller requires no further data to be
transmitted from the slave transmitter.
acknowledged automatically by the master. 1: The received data
byte is acknowledged automatically by the master. This bit-field must
be cleared when the I2C bus controller requires no further data to be
transmitted from the slave transmitter.
0h = Disable acknowledge
1h = Enable acknowledge
2
STOP
W
X
This bit-field determines if the cycle stops at the end of the data
cycle or continues on to a repeated START condition. 0: The
controller does not generate the Stop condition. 1: The controller
generates the Stop condition.
cycle or continues on to a repeated START condition. 0: The
controller does not generate the Stop condition. 1: The controller
generates the Stop condition.
0h = Disable STOP
1h = Enable STOP
1
START
W
X
This bit-field generates the Start or Repeated Start condition. 0: The
controller does not generate the Start condition. 1: The controller
generates the Start condition.
controller does not generate the Start condition. 1: The controller
generates the Start condition.
0h = Disable START
1h = Enable START
0
RUN
W
X
I2C master enable 0: The master is disabled. 1: The master is
enabled to transmit or receive data.
enabled to transmit or receive data.
0h = Disable Master
1h = Enable Master
1403
SWCU117A – February 2015 – Revised March 2015
Inter-Integrated Circuit (I
2
C) Interface
Copyright © 2015, Texas Instruments Incorporated