Texas Instruments CC2650DK Benutzerhandbuch
Memory Interface
22.7 Memory Interface
This section describes the register settings that affect the automated memory interface.
The relevant registers are:
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[I2S:AIFDIRCFG]
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[I2S:AIFDMACFG]
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[I2S:AIFFMTCFG]
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[I2S:AIFWMASKx]
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[I2S:AIFINPTRNEXT]
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[I2S:AIFOUTPTRNEXT]
There are also two observation registers:
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[I2S:AIFINPTR]
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[I2S:AIFOUTPTR]
22.7.1 Word Lengths
The word length on the serial interface and the word length in memory are configured independently:
•
The [I2S:AIFFMTCFG:WORD_LEN] register specifies the maximum number of bits (8 to 24) to transfer
on the serial interface. In single-phase format, this is the exact number of bits per word, while in dual-
phase format this is the maximum number of bits per word.
on the serial interface. In single-phase format, this is the exact number of bits per word, while in dual-
phase format this is the maximum number of bits per word.
•
The [I2S:AIFFMTCFG:MEM_LEN_24] register determines whether words in memory are 16- or 24-bit.
Data written to memory is always aligned to 16 or 24 bits. The [I2S:AIFFMTCFG:MEM_LEN_24] register
configuration determines the behavior of the memory interface as:
configuration determines the behavior of the memory interface as:
•
[I2S:AIFFMTCFG:MEM_LEN_24] = 0: A word is transferred in a single 16-bit transfer. The addresses
written to the [I2S:AIFINPTRNEXT] and [I2S:AIFOUTPTRNEXT] registers must be word-aligned (that
is, even the addresses).
written to the [I2S:AIFINPTRNEXT] and [I2S:AIFOUTPTRNEXT] registers must be word-aligned (that
is, even the addresses).
•
[I2S:AIFFMTCFG:MEM_LEN_24] = 1: A word is transferred in a double-locked transfer consisting of
one 8-bit word and one 16-bit word in the appropriate order. The addresses written to the
[I2S:AIFINPTRNEXT] and [I2S:AIFOUTPTRNEXT] registers do not have to be word-aligned.
one 8-bit word and one 16-bit word in the appropriate order. The addresses written to the
[I2S:AIFINPTRNEXT] and [I2S:AIFOUTPTRNEXT] registers do not have to be word-aligned.
Samples on the serial interface and in memory are always aligned by MSB. If the source is longer than the
destination, the words will be truncated. If the source is shorter than the destination, the words will be
zero-padded.
destination, the words will be truncated. If the source is shorter than the destination, the words will be
zero-padded.
22.7.2 Audio Channels
The audio channel configuration is determined by the [I2S:AIFDIRCFG] and [I2S:AIFWMASKx] registers.
For each ADx pin, the [I2S:AIFWMASKx] register determines whether the channels in a frame are present
in memory or not:
in memory or not:
•
For each frame when [I2S:AIFFMTCFG:DUAL_PHASE] = 0:
–
Input: the [I2S:AIFWMASKx:MASK] register determines whether or not channels are stored in
memory.
memory.
–
Output: the [I2S:AIFWMASKx:MASK] register determines whether or not channels are fetched from
memory. When not fetched from memory, logical 0 will be output on ADx.
memory. When not fetched from memory, logical 0 will be output on ADx.
•
For each frame when [I2S:AIFFMTCFG:DUAL_PHASE] = 1:
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Mono: [I2S:AIFWMASKx:MASK] = 0x01
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Input: Channel 0 is stored to memory.
•
Output: Channel 0 is fetched from memory and repeated for channel 1.
–
Stereo: [I2S:AIFWMASKx:MASK] = 0x03
•
Input: Both channels are stored to memory.
•
Output: Both channels are fetched from memory.
1417
SWCU117A – February 2015 – Revised March 2015
Integrated Interchip Sound (I2S) Module
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