Texas Instruments CC2650DK Benutzerhandbuch
Cortex-M3 Processor Registers
Table 2-105. NVIC_ICER0 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
2
CLRENA2
R/W
X
Writing 0 to this bit has no effect, writing 1 to this bit disables the
interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details).
Reading the bit returns its current enable state.
interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details).
Reading the bit returns its current enable state.
1
CLRENA1
R/W
X
Writing 0 to this bit has no effect, writing 1 to this bit disables the
interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details).
Reading the bit returns its current enable state.
interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details).
Reading the bit returns its current enable state.
0
CLRENA0
R/W
X
Writing 0 to this bit has no effect, writing 1 to this bit disables the
interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details).
Reading the bit returns its current enable state.
interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details).
Reading the bit returns its current enable state.
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SWCU117A – February 2015 – Revised March 2015
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