Texas Instruments CC2650DK Benutzerhandbuch
System
CPU
System RAM
Radio
CPU
L
1
1
L
2
2
CMDR
CMDSTA
IRQs to
Radio CPU
Radio Doorbell
IRQs to
System CPU
Event Fabric
Wake Up IRQ
Controller
4
1
Radio RAM
Radio Doorbell
Figure 23-2. Hardware Support for the HAL
23.2.1 Operational Description
In general, events are signaled on physical lines by a change of the corresponding line from low to high.
Interrupts to the system side are edge interrupts, so the line remains high until the relevant interrupt flags
have been cleared. Interrupts to the radio side are pulse interrupts that remain high for at least one clock
cycle and then go low again.
Interrupts to the system side are edge interrupts, so the line remains high until the relevant interrupt flags
have been cleared. Interrupts to the radio side are pulse interrupts that remain high for at least one clock
cycle and then go low again.
Command and Status Register and Events
Sending commands to the radio is done through the [CMDR] register, while the [CMDSTA] read-only
register provides status back from the radio. The [CMDR] register can only be written while it reads 0,
otherwise, writes are ignored. When the [CMDR] register is 0 and a nonzero value is written to it, the radio
CPU is notified, and the [CMDSTA] register becomes zero. After this, the value written is readable from
the [CMDR] register until the radio CPU has processed the command, at which point it goes back to 0.
register provides status back from the radio. The [CMDR] register can only be written while it reads 0,
otherwise, writes are ignored. When the [CMDR] register is 0 and a nonzero value is written to it, the radio
CPU is notified, and the [CMDSTA] register becomes zero. After this, the value written is readable from
the [CMDR] register until the radio CPU has processed the command, at which point it goes back to 0.
Once the command has been processed by the radio CPU, the [CMDSTA] register will contain a nonzero
status, which is provided at the same instant as the [CMDR] register goes back to 0. At this instant, an
RFCMDACK interrupt occurs. This interrupt is also mapped to the [RFACKIFG] register, which must be
cleared when the interrupt has been processed.
status, which is provided at the same instant as the [CMDR] register goes back to 0. At this instant, an
RFCMDACK interrupt occurs. This interrupt is also mapped to the [RFACKIFG] register, which must be
cleared when the interrupt has been processed.
See
, RFC_DBELL Registers section, for the format of the command and status registers.
23.3 RF Core HAL
The RF core hides the complexity of the radio operations by providing a unified HAL to the system CPU.
23.3.1 Hardware Support
The Radio HAL is supported by hardware, by means of the radio doorbell module in the RF core area and
command descriptors in the system RAM.
command descriptors in the system RAM.
23.3.2 Firmware Support
The RF core accepts a set of high-level primitives. The following sections describe the desired
functionality at a high level.
functionality at a high level.
1457
SWCU117A – February 2015 – Revised March 2015
Radio
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