Texas Instruments CC2650DK Benutzerhandbuch
Radio Registers
23.7.1.5 RFCPEIFG Register (Offset = 10h) [reset = X]
RFCPEIFG is shown in
and described in
Interrupt Flags For Command and Packet Engine Generated Interrupts
Figure 23-13. RFCPEIFG Register
31
30
29
28
27
26
25
24
INTERNAL_ER
BOOT_DONE
MODULES_UN
SYNTH_NO_L
IRQ27
RX_ABORTED
RX_N_DATA_
RX_DATA_WRI
ROR
LOCKED
OCK
WRITTEN
TTEN
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
23
22
21
20
19
18
17
16
RX_ENTRY_D
RX_BUF_FULL
RX_CTRL_AC
RX_CTRL
RX_EMPTY
RX_IGNORED
RX_NOK
RX_OK
ONE
K
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
15
14
13
12
11
10
9
8
IRQ15
IRQ14
IRQ13
BG_COMMAN
TX_BUFFER_C
TX_ENTRY_D
TX_RETRANS
TX_CTRL_ACK
D_SUSPENDE
HANGED
ONE
_ACK
D
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
7
6
5
4
3
2
1
0
TX_CTRL_ACK
TX_CTRL
TX_ACK
TX_DONE
LAST_FG_CO
FG_COMMAN
LAST_COMMA
COMMAND_D
MMAND_DON
D_DONE
ND_DONE
ONE
E
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
Table 23-136. RFCPEIFG Register Field Descriptions
Bit
Field
Type
Reset
Description
31
INTERNAL_ERROR
R/W
X
Interrupt flag 31. The command and packet engine (CPE) has
observed an unexpected error. A reset of the CPE is needed. This
can be done by switching the RF Core power domain off and on in
PRCM:PDCTL1RFC. Write zero to clear flag. Write to one has no
effect.
observed an unexpected error. A reset of the CPE is needed. This
can be done by switching the RF Core power domain off and on in
PRCM:PDCTL1RFC. Write zero to clear flag. Write to one has no
effect.
30
BOOT_DONE
R/W
X
Interrupt flag 30. The command and packet engine (CPE) boot is
finished. Write zero to clear flag. Write to one has no effect.
finished. Write zero to clear flag. Write to one has no effect.
29
MODULES_UNLOCKED
R/W
X
Interrupt flag 29. As part of command and packet engine (CPE) boot
process, it has opened access to RF Core modules and memories.
Write zero to clear flag. Write to one has no effect.
process, it has opened access to RF Core modules and memories.
Write zero to clear flag. Write to one has no effect.
28
SYNTH_NO_LOCK
R/W
X
Interrupt flag 28. The phase-locked loop in frequency synthesizer
has reported loss of lock. Write zero to clear flag. Write to one has
no effect.
has reported loss of lock. Write zero to clear flag. Write to one has
no effect.
27
IRQ27
R/W
X
Interrupt flag 27. Write zero to clear flag. Write to one has no effect.
26
RX_ABORTED
R/W
X
Interrupt flag 26. Packet reception stopped before packet was done.
Write zero to clear flag. Write to one has no effect.
Write zero to clear flag. Write to one has no effect.
25
RX_N_DATA_WRITTEN
R/W
X
Interrupt flag 25. Specified number of bytes written to partial read Rx
buffer. Write zero to clear flag. Write to one has no effect.
buffer. Write zero to clear flag. Write to one has no effect.
24
RX_DATA_WRITTEN
R/W
X
Interrupt flag 24. Data written to partial read Rx buffer. Write zero to
clear flag. Write to one has no effect.
clear flag. Write to one has no effect.
23
RX_ENTRY_DONE
R/W
X
Interrupt flag 23. Rx queue data entry changing state to finished.
Write zero to clear flag. Write to one has no effect.
Write zero to clear flag. Write to one has no effect.
22
RX_BUF_FULL
R/W
X
Interrupt flag 22. Packet received that did not fit in Rx queue. BLE
mode: Packet received that did not fit in the Rx queue. IEEE
802.15.4 mode: Frame received that did not fit in the Rx queue.
Write zero to clear flag. Write to one has no effect.
mode: Packet received that did not fit in the Rx queue. IEEE
802.15.4 mode: Frame received that did not fit in the Rx queue.
Write zero to clear flag. Write to one has no effect.
21
RX_CTRL_ACK
R/W
X
Interrupt flag 21. BLE mode only: LL control packet received with
CRC OK, not to be ignored, then acknowledgement sent. Write zero
to clear flag. Write to one has no effect.
CRC OK, not to be ignored, then acknowledgement sent. Write zero
to clear flag. Write to one has no effect.
1553
SWCU117A – February 2015 – Revised March 2015
Radio
Copyright © 2015, Texas Instruments Incorporated