Texas Instruments CC2650DK Benutzerhandbuch
Radio Registers
23.7.2.1 PWMCLKEN Register (Offset = 0h) [reset = X]
PWMCLKEN is shown in
and described in
.
RF Core Power Management and Clock Enable
Figure 23-18. PWMCLKEN Register
31
30
29
28
27
26
25
24
RESERVED
R-X
23
22
21
20
19
18
17
16
RESERVED
R-X
15
14
13
12
11
10
9
8
RESERVED
RFCTRC
FSCA
PHA
R-X
R/W-X
R/W-X
R/W-X
7
6
5
4
3
2
1
0
RAT
RFERAM
RFE
MDMRAM
MDM
CPERAM
CPE
RFC
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R-1h
Table 23-142. PWMCLKEN Register Field Descriptions
Bit
Field
Type
Reset
Description
31-11
RESERVED
R
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
10
RFCTRC
R/W
X
Enable clock to the RF Core Tracer (RFCTRC) module.
9
FSCA
R/W
X
Enable clock to the Frequency Synthesizer Calibration Accelerator
(FSCA) module.
(FSCA) module.
8
PHA
R/W
X
Enable clock to the Packet Handling Accelerator (PHA) module.
7
RAT
R/W
X
Enable clock to the Radio Timer (RAT) module.
6
RFERAM
R/W
X
Enable clock to the RF Engine RAM module.
5
RFE
R/W
X
Enable clock to the RF Engine (RFE) module.
4
MDMRAM
R/W
X
Enable clock to the Modem RAM module.
3
MDM
R/W
X
Enable clock to the Modem (MDM) module.
2
CPERAM
R/W
X
Enable clock to the Command and Packet Engine (CPE) RAM
module. As part of RF Core initialization, set this bit together with
CPE bit to enable CPE to boot.
module. As part of RF Core initialization, set this bit together with
CPE bit to enable CPE to boot.
1
CPE
R/W
X
Enable processor clock (hclk) to the Command and Packet Engine
(CPE). As part of RF Core initialization, set this bit together with
CPERAM bit to enable CPE to boot.
(CPE). As part of RF Core initialization, set this bit together with
CPERAM bit to enable CPE to boot.
0
RFC
R
1h
Enable essential clocks for the RF Core interface. This includes the
interconnect, the radio doorbell DBELL command interface, the
power management (PWR) clock control module, and bus clock
(sclk) for the CPE. To remove possibility of locking yourself out from
the RF Core, this bit can not be cleared. If you need to disable all
clocks to the RF Core, see the PRCM:RFCCLKG.CLK_EN register.
interconnect, the radio doorbell DBELL command interface, the
power management (PWR) clock control module, and bus clock
(sclk) for the CPE. To remove possibility of locking yourself out from
the RF Core, this bit can not be cleared. If you need to disable all
clocks to the RF Core, see the PRCM:RFCCLKG.CLK_EN register.
1566
Radio
SWCU117A – February 2015 – Revised March 2015
Copyright © 2015, Texas Instruments Incorporated