Texas Instruments CC2650DK Benutzerhandbuch
Cortex-M3 Processor Registers
2.7.4.24 NVIC_IPR7 Register (Offset = 41Ch) [reset = X]
NVIC_IPR7 is shown in
and described in
.
Irq 28 to 31 Priority This register is used to assign a priority from 0 to 255 to each of the available
interrupts. 0 is the highest priority, and 255 is the lowest. The interpretation of the Interrupt Priority
Registers changes based on the setting in AIRCR.PRIGROUP.
interrupts. 0 is the highest priority, and 255 is the lowest. The interpretation of the Interrupt Priority
Registers changes based on the setting in AIRCR.PRIGROUP.
Figure 2-94. NVIC_IPR7 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
PRI_31
PRI_30
PRI_29
PRI_28
R/W-X
R/W-X
R/W-X
R/W-X
Table 2-120. NVIC_IPR7 Register Field Descriptions
Bit
Field
Type
Reset
Description
31-24
PRI_31
R/W
X
Priority of interrupt 31 (See EVENT:CPUIRQSEL31.EV for details).
23-16
PRI_30
R/W
X
Priority of interrupt 30 (See EVENT:CPUIRQSEL30.EV for details).
15-8
PRI_29
R/W
X
Priority of interrupt 29 (See EVENT:CPUIRQSEL29.EV for details).
7-0
PRI_28
R/W
X
Priority of interrupt 28 (See EVENT:CPUIRQSEL28.EV for details).
164
SWCU117A – February 2015 – Revised March 2015
Copyright © 2015, Texas Instruments Incorporated