Texas Instruments CC2650DK Benutzerhandbuch
Cortex-M3 Processor Registers
2.7.4.60 STIR Register (Offset = F00h) [reset = X]
STIR is shown in
and described in
Software Trigger Interrupt
Figure 2-130. STIR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
INTID
W-X
W-0h
Table 2-156. STIR Register Field Descriptions
Bit
Field
Type
Reset
Description
31-9
RESERVED
W
X
Software should not rely on the value of a reserved. Write 0.
8-0
INTID
W
0h
Interrupt ID field. Writing a value to this bit-field is the same as
manually pending an interrupt by setting the corresponding interrupt
bit in an Interrupt Set Pending Register in NVIC_ISPR0 or
NVIC_ISPR1.
manually pending an interrupt by setting the corresponding interrupt
bit in an Interrupt Set Pending Register in NVIC_ISPR0 or
NVIC_ISPR1.
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SWCU117A – February 2015 – Revised March 2015
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