Texas Instruments CC2650DK Benutzerhandbuch
Private peripheral
bus
(internal)
Data
watchpoint
and trace
Interrupts
Debug
Sleep
Instrumentation
trace macrocell
Trace
port
interface
unit
CM3 core
Instructions
Data
Flash
patch and
breakpoint
MPU
Debug
access port
NVIC
Serial wire JTAG
debug port
Bus
matrix
Adv. peripheral
bus
I-code bus
D-code bus
System bus
D-code bus
System bus
ROM
table
Serial
wire
output
trace
port
(SWO)
ARM
Cortex-M3
Overview
The Cortex-M3 processor closely integrates a nested vector interrupt controller (NVIC) to deliver fast
execution of interrupt service routines (ISRs) thereby dramatically reducing interrupt latency. The
hardware stacking of registers and the ability to suspend load-multiple and store-multiple operations
further reduces interrupt latency. Interrupt handlers do not require any assembler stubs, thus removing
code overhead from the ISRs. Tail-chaining optimization also significantly reduces the overhead when
switching from one ISR to another. To optimize low-power designs, the NVIC integrates with the sleep
modes, including deep-sleep mode, which enables the entire device to be rapidly powered down.
execution of interrupt service routines (ISRs) thereby dramatically reducing interrupt latency. The
hardware stacking of registers and the ability to suspend load-multiple and store-multiple operations
further reduces interrupt latency. Interrupt handlers do not require any assembler stubs, thus removing
code overhead from the ISRs. Tail-chaining optimization also significantly reduces the overhead when
switching from one ISR to another. To optimize low-power designs, the NVIC integrates with the sleep
modes, including deep-sleep mode, which enables the entire device to be rapidly powered down.
Figure 2-1. CPU Block Diagram
2.3
Overview
2.3.1 System-Level Interface
The Cortex-M3 processor provides multiple interfaces using AMBA™ technology to provide high-speed,
low-latency memory accesses. The core supports unaligned data accesses and implements atomic bit
manipulation that enables faster peripheral controls, system spinlocks, and thread-safe Boolean data
handling.
low-latency memory accesses. The core supports unaligned data accesses and implements atomic bit
manipulation that enables faster peripheral controls, system spinlocks, and thread-safe Boolean data
handling.
2.3.2 Integrated Configurable Debug
The Cortex-M3 processor implements a complete hardware debug solution through a Serial Wire or JTAG
Debug Port (SWJ-DP) module. SWJ-DP provides a high system visibility of the processor and memory
through a traditional JTAG port. See chapter [reference to debug subsystem chapter] and the ARM®
Debug Interface V5 Architecture Specification for details on SWJ-DP.
Debug Port (SWJ-DP) module. SWJ-DP provides a high system visibility of the processor and memory
through a traditional JTAG port. See chapter [reference to debug subsystem chapter] and the ARM®
Debug Interface V5 Architecture Specification for details on SWJ-DP.
For system trace, the processor integrates an instrumentation trace macrocell (ITM) alongside data
watchpoints and a profiling unit. To enable simple and cost-effective profiling of the system trace events, a
serial wire viewer (SWV) can export a stream of software-generated messages, data trace, and profiling
information through one pin.
watchpoints and a profiling unit. To enable simple and cost-effective profiling of the system trace events, a
serial wire viewer (SWV) can export a stream of software-generated messages, data trace, and profiling
information through one pin.
30
The Cortex-M3 Processor
SWCU117A – February 2015 – Revised March 2015
Copyright © 2015, Texas Instruments Incorporated