Texas Instruments CC2650DK Benutzerhandbuch
Interrupts and Events Registers
4.6.2.55 UDMACH3SSEL Register (Offset = 518h) [reset = X]
UDMACH3SSEL is shown in
and described in
.
Output Selection for DMA Channel 3 SREQ
Figure 4-64. UDMACH3SSEL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
EV
R-X
R-29h
Table 4-70. UDMACH3SSEL Register Field Descriptions
Bit
Field
Type
Reset
Description
31-7
RESERVED
R
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
6-0
EV
R
29h
Read only selection value
29h = SSI0 RX DMA single request, controlled by
SSI0:DMACR.RXDMAE
SSI0:DMACR.RXDMAE
339
SWCU117A – February 2015 – Revised March 2015
Interrupts and Events
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