Texas Instruments CC2650DK Benutzerhandbuch
Interrupts and Events Registers
4.6.2.69 UDMACH10SSEL Register (Offset = 550h) [reset = X]
UDMACH10SSEL is shown in
and described in
Output Selection for DMA Channel 10 SREQ DMA_DONE for the corresponding DMA channel is available
as interrupt on GPT0 as GPT0:RIS.DMABRIS
as interrupt on GPT0 as GPT0:RIS.DMABRIS
Figure 4-78. UDMACH10SSEL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
EV
R-X
R/W-46h
Table 4-84. UDMACH10SSEL Register Field Descriptions
Bit
Field
Type
Reset
Description
31-7
RESERVED
R
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
6-0
EV
R/W
46h
Read/write selection value
0h = Always inactive
46h = Not used tied to 0
4Dh = GPT0A DMA trigger event. Configured by GPT0:DMAEV
4Eh = GPT0B DMA trigger event. Configured by GPT0:DMAEV
4Fh = GPT1A DMA trigger event. Configured by GPT1:DMAEV
50h = GPT1B DMA trigger event. Configured by GPT1:DMAEV
51h = GPT2A DMA trigger event. Configured by GPT2:DMAEV
52h = GPT2B DMA trigger event. Configured by GPT2:DMAEV
53h = GPT3A DMA trigger event. Configured by GPT3:DMAEV
54h = GPT3B DMA trigger event. Configured by GPT3:DMAEV
79h = Always asserted
353
SWCU117A – February 2015 – Revised March 2015
Interrupts and Events
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