Texas Instruments CC2650DK Benutzerhandbuch
Coretex-M3 Core Registers
2.5.2.11 Cortex General-Purpose Register 10 (R10)
Table 2-13. Cortex General-Purpose Register 10 (R10)
Address Offset
Reset
–
Physical Address
Instance
Description
The R10 registers are 32-bit general-purpose registers for data operations and can be accessed from
either privileged or unprivileged mode.
either privileged or unprivileged mode.
Type
R/W
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
DATA
Bits
Field Name
Description
Type
Reset
31:0
DATA
Register data
RW
—
2.5.2.12 Cortex General-Purpose Register 11 (R11)
Table 2-14. Cortex General-Purpose Register 11 (R11)
Address Offset
Reset
–
Physical Address
Instance
Description
The R11 registers are 32-bit general-purpose registers for data operations and can be accessed from
either privileged or unprivileged mode.
either privileged or unprivileged mode.
Type
R/W
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
DATA
Bits
Field Name
Description
Type
Reset
31:0
DATA
Register data
RW
—
2.5.2.13 Cortex General-Purpose Register 12 (R12)
Table 2-15. Cortex General-Purpose Register 12 (R12)
Address Offset
Reset
–
Physical Address
Instance
Description
The Rn registers are 32-bit general-purpose registers for data operations and can be accessed from
either privileged or unprivileged mode.
either privileged or unprivileged mode.
Type
R/W
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
DATA
Bits
Field Name
Description
Type
Reset
31:0
DATA
Register data
RW
—
38
SWCU117A – February 2015 – Revised March 2015
Copyright © 2015, Texas Instruments Incorporated