Texas Instruments CC2650DK Benutzerhandbuch
Test Logic Reset
Run Test Idle
Select DR Scan
Capture DR
Shift DR
Exit 1 DR
Pause DR
Exit 2 DR
Update DR
Select IR Scan
Capture IR
Shift IR
Exit 1 IR
Pause IR
Exit 2 IR
Update IR
TMS=0
TMS=1
TMS=0
TMS=0
TMS=1
TMS=0
TMS=1
TMS=1
TMS=0
TMS=0
TMS=1
TMS=0
TMS=1
TMS=1
TMS=1
TMS=1
TMS=0
TMS=1
TMS=1
TMS=1
TMS=0
TMS=1
TMS=1
TMS=0
TMS=0
TMS=1
TMS=0
TMS=0
TMS=0
TMS=0
TMS=0
TMS=1
Top Level Debug System
The IEEE 1149.1 TAP uses the following signals to support the operation:
•
TCK (Test Clock) – this signal synchronizes the internal state machine operations.
•
TMS (Test Mode Select) – this signal is sampled at the rising edge of TCK to determine the next state.
•
TDI (Test Data In) – this signal represents the data shifted into the test or programming logic of the
device. TDI is sampled at the rising edge of TCK when the internal state machine is in the correct
state.
device. TDI is sampled at the rising edge of TCK when the internal state machine is in the correct
state.
•
TDO (Test Data Out) – this signal represents the data shifted out of the test or programming logic of
the device and is valid on the falling edge of TCK when the internal state machine is in the correct
state.
the device and is valid on the falling edge of TCK when the internal state machine is in the correct
state.
There is no dedicated I/O pin for TRST. The debug subsystem is reset with system-wide resets and
power-on reset.
power-on reset.
The TAP controller, a state machine whose transitions are controlled by the TMS signal, controls the
behavior of the JTAG system.
behavior of the JTAG system.
shows the state-transition diagram for JTAG.
Figure 5-2. JTAG State Machine
Every state has two exits, so all transitions can be controlled by the single TMS signal sampled on TCK.
The two main paths allow for setting or retrieving information from either a data register (DR) or the
instruction register (IR) of the device. The data register depends on the value loaded into the instruction
register.
The two main paths allow for setting or retrieving information from either a data register (DR) or the
instruction register (IR) of the device. The data register depends on the value loaded into the instruction
register.
391
SWCU117A – February 2015 – Revised March 2015
JTAG Interface
Copyright © 2015, Texas Instruments Incorporated