Texas Instruments CC2650DK Benutzerhandbuch
Bit
77
0
TDI
Chip Status
TDO
Access
R
Reset
Unknown
Debug and Shutdown
5.7
Debug and Shutdown
The debugger cannot stay connected in shutdown mode because the power source for debug subsystem
turns off in this mode. This means that entering shutdown will cause abrupt disconnection from the
emulator. To facilitate debugging of the shutdown scenarios, the CC26xx devices have some
considerations:
turns off in this mode. This means that entering shutdown will cause abrupt disconnection from the
emulator. To facilitate debugging of the shutdown scenarios, the CC26xx devices have some
considerations:
•
If a device is in shutdown mode, activity on TCK will cause immediate wakeup.
•
If conditions for HIB are met while entering shutdown mode the device will wake up as soon as it
reaches the shutdown state.
reaches the shutdown state.
NOTE:
If either of these occur, the boot code before handing control to the application code will wait
in a while loop until an I/O wake-up event occurs.
5.8
Debug Features Supported Through WUC TAP
Table 5-23. Debug Features Supported Through WUC TAP
Command
Control Bits
Function
Setting this bit if it is followed by MCU VD
IR 0x01,
CHIP_ERASE_REQ
Reset request through WUC TAP, initiates
Bit 1 in DR[7:0]
chip erase.
IR 0x01,
Setting this bit requests reset of entire
MCU_VD_RESET_REQ
Bit 5 in DR[7:0]
MCU VD.
1: Entering shutdown will be postponed
until JTAG is disconnected.
until JTAG is disconnected.
IR 0x01,
0: Allows the device to enter shutdown
SHUTDOWN_W_JTAG
Bit 6 in DR[7:0]
without waiting for disconnection from
JTAG. Entering shutdown will cause
abrupt disconnection from the emulator.
JTAG. Entering shutdown will cause
abrupt disconnection from the emulator.
Setting this bit requests reset of entire
IR 0x01,
chip. The DEBUGEN bit will remain
SYS_RESET_REQ
Bit 7 in DR[7:0]
asserted after this reset which ensures
HIB after next boot.
HIB after next boot.
IR 0x0C,
Strength and slew control setting for TMS
TMS_PAD_CFG
Bits [5:0] in DR[6:0]
pad.
1: If MCU VD is off, Force Active will
IR 0x0C,
MCU_VD_FORCE_ACTIVE
power up the MCU VD.
Bit 6 in DR[6:0]
0: The application controlls the MCU VD.
1: Prevent JTAG power domain from
IR 0x04,
being powered up from ICEMelter.
JTAG_DO_NOT_PU
Bit 0 in DR[6:0]
0: ICEMelter powers up JTAG power
domain when wake-up conditions are met.
domain when wake-up conditions are met.
1: Do not reset WUC tap when JTAG
IR 0x04
power domain is powered down.
JTAG_DO_NOT_RESET
Bit 4 in DR[6:0]
0: WUC is reset when JTAG power
domain is powered down.
domain is powered down.
5.9
Profiler Register
This register can be used to extract runtime information from the chip with no intrusion to the code
execution. This register resides in the TEST TAP. Refer to
execution. This register resides in the TEST TAP. Refer to
for more details
Figure 5-12. Profiler Register
409
SWCU117A – February 2015 – Revised March 2015
JTAG Interface
Copyright © 2015, Texas Instruments Incorporated