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Introduction
6.1.4.2
Clocks in MCU_VD
AON_WUC supports MCU_VD with a clock that is divided and gated by PRCM before being distributed to
all modules in MCU_VD.
all modules in MCU_VD.
shows which registers in PRCM defines division and gate control for
all module clocks. When no BUS transactions can occur, hardware will automatically gate the SYSBUS
clock.
These conditions must true to gate the SYSBUS:
clock.
These conditions must true to gate the SYSBUS:
•
System CPU in deepsleep mode
•
[PRCM.SECDMACLKGDS.DMA_CLK_EN] = 0
•
[PRCM.SECDMACLKGDS.SEC_CLK_EN] = 0
•
RFCORE FW does not require bus access
The SYSBUS clock may run even when the system CPU is in deepsleep mode when either DMA, SEC, or
RFCORE needs an active interconnect.
RFCORE needs an active interconnect.
MCU_AON has two clocks, an INFRASTRUCTURE clock that always runs and an PERBUSULL clock that
is identical to the INFRASTRUCTURE clock whenever the SYSBUS clock is running. When the SYSBUS
clock is gated, the PERBUSULL clock is automatically gated. INFRASTRUCTURE and PERBUSULL
clocks are automatically controlled to run at a maximum of half the clock frequency of SCLK_HF,
regardless of the settings in [PRCM:INFCLKDIVR/S/DS].
is identical to the INFRASTRUCTURE clock whenever the SYSBUS clock is running. When the SYSBUS
clock is gated, the PERBUSULL clock is automatically gated. INFRASTRUCTURE and PERBUSULL
clocks are automatically controlled to run at a maximum of half the clock frequency of SCLK_HF,
regardless of the settings in [PRCM:INFCLKDIVR/S/DS].
420
Power, Reset, and Clock Management
SWCU117A – February 2015 – Revised March 2015
Copyright © 2015, Texas Instruments Incorporated