Texas Instruments CC2650DK Benutzerhandbuch
PRCM Registers
6.2.1.3
INFRCLKDIVDS Register (Offset = 8h) [reset = X]
INFRCLKDIVDS is shown in
and described in
.
Infrastructure Clock Division Factor For DeepSleep Mode
Figure 6-9. INFRCLKDIVDS Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESERVED
R-X
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESERVED
RATIO
R-X
R/W-X
Table 6-11. INFRCLKDIVDS Register Field Descriptions
Bit
Field
Type
Reset
Description
31-2
RESERVED
R
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
1-0
RATIO
R/W
X
Division rate for clocks driving modules in the MCU_AON domain
when system CPU is in seepsleep mode. Division ratio affects both
infrastructure clock and perbusull clock.
when system CPU is in seepsleep mode. Division ratio affects both
infrastructure clock and perbusull clock.
0h = Divide by 1
1h = Divide by 2
2h = Divide by 8
3h = Divide by 32
432
Power, Reset, and Clock Management
SWCU117A – February 2015 – Revised March 2015
Copyright © 2015, Texas Instruments Incorporated