Texas Instruments CC2650DK Benutzerhandbuch
PRCM Registers
6.2.1.16 GPTCLKGDS Register (Offset = 5Ch) [reset = X]
GPTCLKGDS is shown in
and described in
GPT Clock Gate For Deep Sleep Mode
Figure 6-22. GPTCLKGDS Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESERVED
R-X
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESERVED
CLK_EN
R-X
R/W-X
Table 6-24. GPTCLKGDS Register Field Descriptions
Bit
Field
Type
Reset
Description
31-4
RESERVED
R
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
3-0
CLK_EN
R/W
X
Each bit below has the following meaning: 0: Disable clock 1: Enable
clock ENUMs can be combined For changes to take effect,
CLKLOADCTL.LOAD needs to be written
clock ENUMs can be combined For changes to take effect,
CLKLOADCTL.LOAD needs to be written
1h = Enable clock for GPT0
2h = Enable clock for GPT1
4h = Enable clock for GPT2
8h = Enable clock for GPT3
445
SWCU117A – February 2015 – Revised March 2015
Power, Reset, and Clock Management
Copyright © 2015, Texas Instruments Incorporated