Texas Instruments CC2650DK Benutzerhandbuch
PRCM Registers
6.2.4.14 STAT0 Register (Offset = 34h) [reset = X]
STAT0 is shown in
and described in
Status 0 This register contains status signals from OSC_DIG
Figure 6-94. STAT0 Register
31
30
29
28
27
26
25
24
SPARE31
SCLK_LF_SRC
SCLK_HF_SR
RESERVED
C
R-X
R-X
R-X
R-X
23
22
21
20
19
18
17
16
RESERVED
RCOSC_HF_E
RCOSC_LF_E
XOSC_LF_EN
CLK_DCDC_R
CLK_DCDC_R
SCLK_HF_LOS SCLK_LF_LOS
N
N
DY
DY_ACK
S
S
R-X
R-X
R-X
R-X
R-X
R-X
R-X
R-X
15
14
13
12
11
10
9
8
XOSC_HF_EN
RESERVED
XB_48M_CLK_
RESERVED
XOSC_HF_LP_
XOSC_HF_HP
RESERVED
ADC_THMET
EN
BUF_EN
_BUF_EN
R-X
R-X
R-X
R-X
R-X
R-X
R-X
R-X
7
6
5
4
3
2
1
0
ADC_DATA_R
ADC_DATA
PENDINGSCL
EADY
KHFSWITCHIN
G
R-X
R-X
R-X
Table 6-99. STAT0 Register Field Descriptions
Bit
Field
Type
Reset
Description
31
SPARE31
R
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
30-29
SCLK_LF_SRC
R
X
Indicates source for the sclk_lf
0h = Low frequency clock derived from High Frequency RCOSC
1h = Low frequency clock derived from High Frequency XOSC
2h = Low frequency RCOSC
3h = Low frequency XOSC
28
SCLK_HF_SRC
R
X
Indicates source for the sclk_hf
0h = High frequency RCOSC clk
1h = High frequency XOSC
27-23
RESERVED
R
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
22
RCOSC_HF_EN
R
X
RCOSC_HF_EN
21
RCOSC_LF_EN
R
X
RCOSC_LF_EN
20
XOSC_LF_EN
R
X
XOSC_LF_EN
19
CLK_DCDC_RDY
R
X
CLK_DCDC_RDY
18
CLK_DCDC_RDY_ACK
R
X
CLK_DCDC_RDY_ACK
17
SCLK_HF_LOSS
R
X
Indicates sclk_hf is lost
16
SCLK_LF_LOSS
R
X
Indicates sclk_lf is lost
15
XOSC_HF_EN
R
X
Indicates that XOSC_HF is enabled.
14
RESERVED
R
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
13
XB_48M_CLK_EN
R
X
Indicates that the 48MHz clock from the DOUBLER is enabled. It will
be enabled if 24 or 48 MHz chrystal is used (enabled in doulbler
bypass for the 48MHz chrystal).
be enabled if 24 or 48 MHz chrystal is used (enabled in doulbler
bypass for the 48MHz chrystal).
524
Power, Reset, and Clock Management
SWCU117A – February 2015 – Revised March 2015
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