Texas Instruments CC2650DK Benutzerhandbuch
Factory Configuration (FCFG)
9.2.1.8
CONFIG_SYNTH_DIV6 Register (Offset = E0h) [reset = FFFFFFFFh]
CONFIG_SYNTH_DIV6 is shown in
and described in
.
Configuration of Synthesizer in Divide-by-6 Mode Divide-by-6 mode is only available for CC13xx.
Figure 9-29. CONFIG_SYNTH_DIV6 Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESERVED
RFC_MDM_DEMIQMC0
R-Fh
R-FFFFh
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RFC_MDM_DEMIQMC0
LDOVCO_TRIM_OUTPUT
SLDO_TRIM_OUTPUT
R-FFFFh
R-3Fh
R-3Fh
Table 9-31. CONFIG_SYNTH_DIV6 Register Field Descriptions
Bit
Field
Type
Reset
Description
31-28
RESERVED
R
Fh
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
27-12
RFC_MDM_DEMIQMC0
R
FFFFh
Trim value for RFC_MDM:DEMIQMC0.GAINFACTOR and
RFC_MDM:DEMIQMC0.PHASEFACTOR Value is read by RF Core
ROM FW during RF Core initialization.
RFC_MDM:DEMIQMC0.PHASEFACTOR Value is read by RF Core
ROM FW during RF Core initialization.
11-6
LDOVCO_TRIM_OUTPU
R
3Fh
Trim value for ADI_1_SYNTH:VCOLDOCTL1.TRIM_OUT. Value is
T
read by RF Core ROM FW during RF Core initialization.
5-0
SLDO_TRIM_OUTPUT
R
3Fh
Trim value for ADI_1_SYNTH:SLDOCTL1.TRIM_OUT. Value is read
by RF Core ROM FW during RF Core initialization.
by RF Core ROM FW during RF Core initialization.
723
SWCU117A – February 2015 – Revised March 2015
Device Configuration
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