Texas Instruments CC2650DK Benutzerhandbuch
Factory Configuration (FCFG)
9.2.1.13 CONFIG_MISC_ADC_DIV5 Register (Offset = F4h) [reset = FFFFFFFFh]
CONFIG_MISC_ADC_DIV5 is shown in
and described in
Configuration of IFADC in Divide-by-5 Mode Divide-by-5 mode is only available for CC13xx.
Figure 9-34. CONFIG_MISC_ADC_DIV5 Register
31
30
29
28
27
26
25
24
RESERVED
R-7FFFh
23
22
21
20
19
18
17
16
RESERVED
RSSI_OFFSET
R-7FFFh
R-FFh
15
14
13
12
11
10
9
8
RSSI_OFFSET
QUANTCTLTH
RES
R-FFh
R-7h
7
6
5
4
3
2
1
0
QUANTCTLTHRES
DACTRIM
R-7h
R-3Fh
Table 9-36. CONFIG_MISC_ADC_DIV5 Register Field Descriptions
Bit
Field
Type
Reset
Description
31-17
RESERVED
R
7FFFh
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
16-9
RSSI_OFFSET
R
FFh
Value for RSSI measured in production test. Value is read by RF
Core ROM FW during RF Core initialization.
Core ROM FW during RF Core initialization.
8-6
QUANTCTLTHRES
R
7h
Trim value for ADI_0_RF:IFADCQUANT0.TH. Value is read by RF
Core ROM FW during RF Core initialization.
Core ROM FW during RF Core initialization.
5-0
DACTRIM
R
3Fh
Trim value for ADI_0_RF:IFADCDAC.TRIM. Value is read by RF
Core ROM FW during RF Core initialization.
Core ROM FW during RF Core initialization.
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Device Configuration
SWCU117A – February 2015 – Revised March 2015
Copyright © 2015, Texas Instruments Incorporated