Texas Instruments CC2650DK Benutzerhandbuch
Cortex-M3 Processor Registers
2.7.1.23 STIM22 Register (Offset = 58h) [reset = 0h]
STIM22 is shown in
and described in
Stimulus Port 22
Figure 2-26. STIM22 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
STIM22
R/W-0h
Table 2-49. STIM22 Register Field Descriptions
Bit
Field
Type
Reset
Description
31-0
STIM22
R/W
0h
A write to this location causes data to be written into the FIFO if
TER.STIMENA22 is set. Reading from the stimulus port returns the
FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface
does not provide an atomic read-modify-write, so it's users
responsibility to ensure exclusive read-modify-write if this ITM port is
used concurrently by interrupts or other threads.
TER.STIMENA22 is set. Reading from the stimulus port returns the
FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface
does not provide an atomic read-modify-write, so it's users
responsibility to ensure exclusive read-modify-write if this ITM port is
used concurrently by interrupts or other threads.
74
SWCU117A – February 2015 – Revised March 2015
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