Texas Instruments CC2650DK Benutzerhandbuch
Factory Configuration (FCFG)
9.2.1.54 CONFIG_IF_ADC Register (Offset = 34Ch) [reset = X]
CONFIG_IF_ADC is shown in
and described in
.
Configuration of IF_ADC
Figure 9-75. CONFIG_IF_ADC Register
31
30
29
28
27
26
25
24
FF2ADJ
FF3ADJ
R-3h
R-4h
23
22
21
20
19
18
17
16
INT3ADJ
FF1ADJ
R-6h
R-X
15
14
13
12
11
10
9
8
AAFCAP
INT2ADJ
IFDIGLDO_TRIM_OUTPUT
R-3h
R-Dh
R-0h
7
6
5
4
3
2
1
0
IFDIGLDO_TRIM_OUTPUT
IFANALDO_TRIM_OUTPUT
R-0h
R-0h
Table 9-77. CONFIG_IF_ADC Register Field Descriptions
Bit
Field
Type
Reset
Description
31-28
FF2ADJ
R
3h
Trim value for ADI_0_RF:IFADCLFCFG1.FF2ADJ. Value is read by
RF Core ROM FW during RF Core initialization.
RF Core ROM FW during RF Core initialization.
27-24
FF3ADJ
R
4h
Trim value for ADI_0_RF:IFADCLFCFG1.FF3ADJ. Value is read by
RF Core ROM FW during RF Core initialization.
RF Core ROM FW during RF Core initialization.
23-20
INT3ADJ
R
6h
Trim value for ADI_0_RF:IFADCLFCFG0.INT3ADJ. Value is read by
RF Core ROM FW during RF Core initialization.
RF Core ROM FW during RF Core initialization.
19-16
FF1ADJ
R
X
Trim value for ADI_0_RF:IFADCLFCFG0.FF1ADJ. Value is read by
RF Core ROM FW during RF Core initialization.
RF Core ROM FW during RF Core initialization.
15-14
AAFCAP
R
3h
Trim value for ADI_0_RF:IFADCCTL0.AAFCAP. Value is read by RF
Core ROM FW during RF Core initialization.
Core ROM FW during RF Core initialization.
13-10
INT2ADJ
R
Dh
Trim value for ADI_0_RF:IFADCCTL0.INT2ADJ. Value is read by RF
Core ROM FW during RF Core initialization.
Core ROM FW during RF Core initialization.
9-5
IFDIGLDO_TRIM_OUTPU R
0h
Trim value for ADI_0_RF:IFDLDO2.TRIM_OUT. Value is read by RF
T
Core ROM FW during RF Core initialization.
Reset holds trim value from production test.
4-0
IFANALDO_TRIM_OUTP
R
0h
Trim value for ADI_0_RF:IFALDO2.TRIM_OUT. Value is read by RF
UT
Core ROM FW during RF Core initialization.
Reset holds trim value from production test.
771
SWCU117A – February 2015 – Revised March 2015
Device Configuration
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