Texas Instruments CC2650DK Benutzerhandbuch
Factory Configuration (FCFG)
9.2.1.67 CONFIG_MISC_ADC Register (Offset = 380h) [reset = FFFC014Dh]
CONFIG_MISC_ADC is shown in
and described in
.
Configuration of IFADC in Divide-by-2 Mode
Figure 9-88. CONFIG_MISC_ADC Register
31
30
29
28
27
26
25
24
RESERVED
R-3FFFh
23
22
21
20
19
18
17
16
RESERVED
RSSITRIMCOM RSSI_OFFSET
PLETE_N
R-3FFFh
R-0h
R-0h
15
14
13
12
11
10
9
8
RSSI_OFFSET
QUANTCTLTH
RES
R-0h
R-5h
7
6
5
4
3
2
1
0
QUANTCTLTHRES
DACTRIM
R-5h
R-Dh
Table 9-90. CONFIG_MISC_ADC Register Field Descriptions
Bit
Field
Type
Reset
Description
31-18
RESERVED
R
3FFFh
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
17
RSSITRIMCOMPLETE_N
R
0h
Status of RSSI trim 0: Trimmed 1: Not trimmed
Reset holds trim value from production test.
16-9
RSSI_OFFSET
R
0h
Value for RSSI measured in production test. Value is read by RF
Core ROM FW during RF Core initialization.
Core ROM FW during RF Core initialization.
Reset holds trim value from production test.
8-6
QUANTCTLTHRES
R
5h
Trim value for ADI_0_RF:IFADCQUANT0.TH. Value is read by RF
Core ROM FW during RF Core initialization.
Core ROM FW during RF Core initialization.
5-0
DACTRIM
R
Dh
Trim value for ADI_0_RF:IFADCDAC.TRIM. Value is read by RF
Core ROM FW during RF Core initialization.
Core ROM FW during RF Core initialization.
784
Device Configuration
SWCU117A – February 2015 – Revised March 2015
Copyright © 2015, Texas Instruments Incorporated