Texas Instruments CC2650DK Benutzerhandbuch
Factory Configuration (FCFG)
9.2.1.74 PWD_CURR_50C Register (Offset = 3A4h) [reset = 1218A20Dh]
PWD_CURR_50C is shown in
and described in
Power Down Current Control 50C
Figure 9-95. PWD_CURR_50C Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DELTA_CACHE_REF
DELTA_RFMEM_RET
R-12h
R-18h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DELTA_XOSC_LPM
BASELINE
R-A2h
R-Dh
Table 9-97. PWD_CURR_50C Register Field Descriptions
Bit
Field
Type
Reset
Description
31-24
DELTA_CACHE_REF
R
12h
Additional maximum current, in units of 1uA, with cache retention
23-16
DELTA_RFMEM_RET
R
18h
Additional maximum current, in 1uA units, with RF memory retention
15-8
DELTA_XOSC_LPM
R
A2h
Additional maximum current, in units of 1uA, with XOSC_HF on in
low-power mode
low-power mode
7-0
BASELINE
R
Dh
Worst-case baseline maximum powerdown current, in units of 0.5uA
791
SWCU117A – February 2015 – Revised March 2015
Device Configuration
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