Texas Instruments CC2650DK Benutzerhandbuch
Cryptography Registers
10.2.1.16 AESKEY2_0 to AESKEY2_3 Register (Offset = 500h to 50Ch) [reset = X]
AESKEY2_0 to AESKEY2_3 is shown in
and described in
Clear AES_KEY2/GHASH Key
Figure 10-18. AESKEY2_0 to AESKEY2_3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
KEY2
W-X
Table 10-26. AESKEY2_0 to AESKEY2_3 Register Field Descriptions
Bit
Field
Type
Reset
Description
31-0
KEY2
W
X
AESKEY2.* bits 31+x:0+x or AES_GHASH_H.* bits 31+x:0+x, where
x = 0, 32, 64, 96 ordered from the LSW entry of this 4-deep register
array. The interpretation of this field depends on the crypto operation
mode.
x = 0, 32, 64, 96 ordered from the LSW entry of this 4-deep register
array. The interpretation of this field depends on the crypto operation
mode.
841
SWCU117A – February 2015 – Revised March 2015
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