Texas Instruments CC2650DK Benutzerhandbuch
Cortex-M3 Processor Registers
2.7.2.6
LSUCNT Register (Offset = 14h) [reset = X]
LSUCNT is shown in
and described in
LSU Count This register is used to count the total number of cycles during which the processor is
processing an LSU operation beyond the first cycle.
processing an LSU operation beyond the first cycle.
Figure 2-46. LSUCNT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
LSUCNT
R/W-X
R/W-0h
Table 2-70. LSUCNT Register Field Descriptions
Bit
Field
Type
Reset
Description
31-8
RESERVED
R/W
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
7-0
LSUCNT
R/W
0h
LSU counter. This counts the total number of cycles that the
processor is processing an LSU operation. The initial execution cost
of the instruction is not counted. For example, an LDR that takes two
cycles to complete increments this counter one cycle. Equivalently,
an LDR that stalls for two cycles (i.e. takes four cycles to execute),
increments this counter three times. An event is emitted on counter
overflow (every 256 cycles). This counter initializes to 0 when it is
enabled using CTRL.LSUEVTENA.
processor is processing an LSU operation. The initial execution cost
of the instruction is not counted. For example, an LDR that takes two
cycles to complete increments this counter one cycle. Equivalently,
an LDR that stalls for two cycles (i.e. takes four cycles to execute),
increments this counter three times. An event is emitted on counter
overflow (every 256 cycles). This counter initializes to 0 when it is
enabled using CTRL.LSUEVTENA.
99
SWCU117A – February 2015 – Revised March 2015
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