Texas Instruments DP130 Single-Source Evaluation Module DP130SSEVM DP130SSEVM Datenbogen
Produktcode
DP130SSEVM
Driver
V
Iterm
50 W
50 W
Receiver
D+
D-
V
D+
V
D-
V
ID
V
ICM
= (V
D+
+ V
D-
)
Y
Z
V
Y
V
Z
V
OD
= V
Y
- V
Z
100pF
100pF
0V to 2V
50 W
50 W
V
ID
= V
D+
- V
D-
2
V
OCM
= (V
Y
+ V
Z
)
2
V
OCM
DV
OCM
(ss)
V
OCM
(pp)
D+
D-
0V
20%
t
F
t
R
80%
0%
100%
V
OD
SLLSE57D – APRIL 2011 – REVISED JULY 2013
MAIN LINK ELECTRICAL CHARACTERISTICS (continued)
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Change in steady state output
ΔV
OCM(SS)
common-mode voltage between
Tested in compliance to section 3.10 in CTS 1.1a
10
mV
PP
logic levels
20
mV
RMS
V
OCM(PP)
Output common-mode noise
HBR2
30
mV
RMS
V
SQUELCH
Squelch threshold voltage
Programable via I
2
C; default at 80mVpp typical
80
mV
PP
I
TXSHORT
Short circuit current limit
Main Link outputs shorted to GND
50
mA
MAIN LINK SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
PD
Propagation delay time
See
300
ps
t
SK(1)
Intra-pair output skew
Signal input skew = 0ps; d
R
= 2.7Gbps, V
PRE
= 0dB,
20
ps
800mVp-p, D10.2 clock pattern at device input; See
t
SK(2)
Inter-pair output skew
100
ps
V
OD(L0)
; V
PRE(L0)
; EQ = 8dB; clean source; minimum input
Δt
jit
Total peak-to-peak residual jitter and output cabling; 1.62Gbps, 2.7Gbps, and 5.4Gbps
15
ps
PRBS7 data pattern.
Time from active DP signal turned off to ML output off with
t
sq_enter
Squelch entry time
10
120
μs
noise floor minimized
t
sq_exit
Squelch exit time
Time from DP signal on to ML output on
0
1
μs
Figure 8. Main Link Test Circuit
Copyright © 2011–2013, Texas Instruments Incorporated
13
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