Texas Instruments DP130 Single-Source Evaluation Module DP130SSEVM DP130SSEVM Datenbogen
Produktcode
DP130SSEVM
SLLSE57D – APRIL 2011 – REVISED JULY 2013
Table 8. SN75DP130 Local I
2
C Control and Status Registers (continued)
ACCESS
(
ADDRESS
BIT(S)
DESCRIPTION
1)
I2C_SOFT_RESET. Writing a one to this register resets all I
2
C registers to default values.
7
WO
Writing a zero to this register has no effect. Reads from this register return zero.
1Bh
DPCD_RESET. Writing a one to this register resets the DPCD register bits (corresponding to
6
DPCD addresses 103h – 106h, the AEQ_Lx_LANEy_SET bits). Writing a zero to this register
has no effect. Reads from this register return zero.
has no effect. Reads from this register return zero.
DPCD_ADDR_HIGH. This value maps to bits 19:16 of the 20-bit DPCD register address
1Ch
3:0
RW
accessed through the DPCD_DATA register.
DPCD_ADDR_MID. This value maps to bits 15:8 of the 20-bit DPCD register address
1Dh
7:0
RW
accessed through the DPCD_DATA register.
DPCD_ADDR_LOW. This value maps to bits 7:0 of the 20-bit DPCD register address
1Eh
7:0
RW
accessed through the DPCD_DATA register.
DPCD_DATA. This register contains the data to write into or read from the DPCD register
1Fh
7:0
RW
addressed by DPCD_ADDR_HIGH, DPCD_ADDR_MID, and DPCD_ADDR_LOW.
DEV_ID_REV. This field identifies the device and revision.
7:1
RO
0000000 – SN75DP130 Revision 0
20h
BIT_INVERT. The value read from this field is the inverse of that written.
0
RW
Default read value is zero.
21h
7:0
TI_TEST. These registers shall not be modified.
RW
22h – 27h
7:0
TI_TEST_RESERVED. These read only registers are reserved for test; writes are ignored.
RO
32
Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: