Texas Instruments SRC4382 Evaluation Module (EVM) and USB motherboard SRC4382EVM-PDK SRC4382EVM-PDK Datenbogen
Produktcode
SRC4382EVM-PDK
www.ti.com
DIR_OUT
SRC_OU
T
PORT_A_IN
PORT_B_IN
Audio Serial
Port A
Audio Serial
Port B
Digital
Interface
Receiver (DIR)
Digital
Interface
Transmitter
(DIT)
Asynchronous
Sample Rate
Converter
(SRC)
TX+
TX
-
SDINA
SDOUTA
LRCKA
BC A
K
SDINB
SDOUTB
LRCKB
BC B
K
CPM
CS or A0
CCLK or SCL
CDIN or
1
A
CDOUT or SDA
INT
RST
Host
Interface
(SPI or I C)
2
and
Gene a
r l-
Purp s
o e
Outputs
Master
Cl ck
o
Distribution
MC K
L
RXCKI
From RXCKO
GP
1
O
GP
2
O
GP
3
O
GP
4
O
AESOUT
RXCKO
LOCK
RX +
2
RX
-
2
RX +
3
RX
-
3
RX +
4
RX
-
4
RX +
1
RX
-
1
RDY
MU E
T
BLS
SY C
N
PORTA
PORTB
DIR
DIT
SRC
Control and Status
Registers
DIR C and U
Data Buffers
DIT C and U
Data Buffers
SRC4382
Power
VDD18
DGND1
VDD33
DGND2
VIO
DGND3
VCC
AG D
N
BG D
N
Internally Tied
to Substrate
RESET OPERATION
SBFS030C – JANUARY 2006 – REVISED SEPTEMBER 2007
shows a simplified functional block diagram for the SRC4382. Additional details for each function block
will be covered in respective sections of this datasheet.
Figure 59. Functional Block Diagram
The SRC4382 includes an asynchronous active low reset input, RST (pin 24), which may be used to initialize the
internal logic at any time. The reset sequence forces all registers and buffers to their default settings. The reset
low pulse width must be a minimum of 500ns in length. The user should not attempt a write or read operation
using either the SPI or I
internal logic at any time. The reset sequence forces all registers and buffers to their default settings. The reset
low pulse width must be a minimum of 500ns in length. The user should not attempt a write or read operation
using either the SPI or I
2
C port for at least 500
μ
s after the rising edge of RST. See
for the reset timing
sequence of the SRC4382.
In addition to reset input, the RESET bit in control register 0x01 may be used to force an internal reset, whereby
all registers and buffers are forced to their default settings. Refer to the
all registers and buffers are forced to their default settings. Refer to the
section for details
regarding the RESET bit function.
Upon reset initialization, all functional blocks of the SRC4382 default to the powered-down state, with the
exception of the SPI or I
exception of the SPI or I
2
C host interface and the corresponding control registers. The user may then program
the SRC4382 to the desired configuration, and then release the desired function blocks from the power-down
state utilizing the corresponding bits in control register 0x01.
state utilizing the corresponding bits in control register 0x01.
Copyright © 2006–2007, Texas Instruments Incorporated
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