Texas Instruments SRC4382 Evaluation Module (EVM) and USB motherboard SRC4382EVM-PDK SRC4382EVM-PDK Datenbogen
Produktcode
SRC4382EVM-PDK
www.ti.com
AUDIO SERIAL PORT OPERATION
Master
Clock
Source
Master
Mo e
d
Clock
Generation
Serial
Input
Serial
Output
MC K
L
RXCKI
RXCKO
Audio Data
Internal Clocks
Port A
Port B
DIR
SRC
OUTS[1:0]
MU E
T
F
T[1:
M
0]
M/S
DIV 1:
[
0]
CLK 1:
[
0]
SD N
I A (pin 39) or SDINB (pin 4 )
6
LRCKA (pin 3 ) or
8
LRCKB ( i
47)
p n
BCKA (pin 37) or BCKB (pin 48)
SDOUTA (pin 40) or SDOUTB (pin 45)
Da a
t
Source
SBFS030C – JANUARY 2006 – REVISED SEPTEMBER 2007
The SRC4382 includes two audio serial ports, Port A and Port B. Both ports are 4-wire synchronous serial
interfaces, supporting simultaneous input and output operation. Since each port has only one pair of left/right
word and bit clocks, the input and output sampling rates are identical. A simplified block diagram is shown in
interfaces, supporting simultaneous input and output operation. Since each port has only one pair of left/right
word and bit clocks, the input and output sampling rates are identical. A simplified block diagram is shown in
.
The audio serial ports may be operated at sampling rates up to 216kHz, and support audio data word lengths up
to 24 bits. Philips I
to 24 bits. Philips I
2
S, Left-Justified, and Right-Justified serial data formats are supported. Refer to
The left/right word clock (LRCKA or LRCKB) and the bit clock (BCKA or BCKB) may be configured for either
Master or Slave mode operation. In Master mode these clocks are outputs, derived from the selected master
clock source using internal clock dividers. The master clock source may be 128, 256, 384, or 512 times the audio
input/output sampling rate, with the clock divider being selected using control register bits for each port. In Slave
mode the left/right word and bit clocks are inputs, being sourced from an external audio device acting as the
serial bus master.
Master or Slave mode operation. In Master mode these clocks are outputs, derived from the selected master
clock source using internal clock dividers. The master clock source may be 128, 256, 384, or 512 times the audio
input/output sampling rate, with the clock divider being selected using control register bits for each port. In Slave
mode the left/right word and bit clocks are inputs, being sourced from an external audio device acting as the
serial bus master.
The LRCKA or LRCKB clocks operate at the input/output sampling rate, f
S
. The BCKA and BCKB clock rates are
fixed at 64 times the left/right word clock rate in Master mode. For Slave mode, the minimum BCKA and BCKB
clock rate is determined by the audio data word length multiplied by two, since there are two audio data channels
per left/right word clock period. For example, if the audio data word length is 24 bits, the bit clock rate must be at
least 48 times the left/right word clock rate, allowing one bit clock period for each data bit in the serial bit stream.
clock rate is determined by the audio data word length multiplied by two, since there are two audio data channels
per left/right word clock period. For example, if the audio data word length is 24 bits, the bit clock rate must be at
least 48 times the left/right word clock rate, allowing one bit clock period for each data bit in the serial bit stream.
Serial audio data is clocked into the port on the rising edge of the bit clock, while data is clocked out of the port
on the falling edge of the bit clock. Refer to the
on the falling edge of the bit clock. Refer to the
Audio Serial Ports table for parametric
information and
for a timing diagram related to audio serial port operation.
The audio serial ports are configured using control registers 0x03 through 0x06. Refer to the
section for descriptions of the control register bits.
Figure 61. Audio Serial Port Block Diagram
Copyright © 2006–2007, Texas Instruments Incorporated
25
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