Texas Instruments SRC4382 Evaluation Module (EVM) and USB motherboard SRC4382EVM-PDK SRC4382EVM-PDK Datenbogen
Produktcode
SRC4382EVM-PDK
www.ti.com
De-Emph s
a is
F te
i
r
l
Interpolation
F te
i
r
l
Decimation
F te
i
r
l
Re-Sampler
Rate
Es mator
ti
f
SIN
f
SOUT
R fere
e
nce Clock
P rt A
o
P rt B
o
DIR
Audio Data Output
INT_ Y
S NC
From Port A, Port B, or DIT
SRCIS[1:0]
DEM[ :
1 0]
AUTODEM
IGRP[1:0]
SRI[ :
4 0]
SRF[10:0]
R
I
A
O
T
RDY
(pin 15)
M TE (
U
pin 14)
DDN
T
C
R
K
A
AL[7:0]
AR[7:0]
OWL[ :
1 0]
MC K
L
R
K
X
I
C
R
K
X
O
C
SRCCLK[1 0
: ]
SBFS030C – JANUARY 2006 – REVISED SEPTEMBER 2007
input-to-output sampling ratio range. The input and output data sources may be completely asynchronous to one
another; synchronous operation is also supported. The input-to-output sampling ratio is determined automatically
using internal rate estimation logic, with the re-sampler being updated in real time without the need for
programming. The SRC supports input and output sampling rates up to 216kHz, with audio data word lengths up
to 24 bits. A functional block diagram for the SRC is shown in
another; synchronous operation is also supported. The input-to-output sampling ratio is determined automatically
using internal rate estimation logic, with the re-sampler being updated in real time without the need for
programming. The SRC supports input and output sampling rates up to 216kHz, with audio data word lengths up
to 24 bits. A functional block diagram for the SRC is shown in
Figure 72. Asynchronous Sample Rate Converter (SRC) Functional Block Diagram
The SRC receives a digital audio input from one of three data sources: Port A, Port B, or the DIR. By default,
Port A is selected as the input source for the SRC. The output of the SRC may be connected to Port A, Port B,
and/or the DIT.
Port A is selected as the input source for the SRC. The output of the SRC may be connected to Port A, Port B,
and/or the DIT.
The SRC requires a reference clock, which may be sourced from either the MCLK (pin 25) or RXCKI (pin 13)
clock inputs, or from the RXCKO recovered master clock output from the DIR block. The reference clock is
utilized by the rate estimator to determine the input-to-output sampling ratio. By default, MCLK is selected as the
reference clock source for the SRC.
clock inputs, or from the RXCKO recovered master clock output from the DIR block. The reference clock is
utilized by the rate estimator to determine the input-to-output sampling ratio. By default, MCLK is selected as the
reference clock source for the SRC.
As part of the SRC rate estimation and re-sampling functions, two digital servo loops are employed, one for the
input side and one for the output side. The servo loops operate in two modes: Fast and Slow. When a change in
one or both of the sampling rates occurs, the servo loop(s) enter(s) Fast mode operation. When a servo loop has
settled in Fast mode, it will then switch to Slow mode. When both the input and output servo loops have switched
to Slow mode, the RDY output (pin 15) is forced low, indicating that the SRC has completed the rate estimation
process.
input side and one for the output side. The servo loops operate in two modes: Fast and Slow. When a change in
one or both of the sampling rates occurs, the servo loop(s) enter(s) Fast mode operation. When a servo loop has
settled in Fast mode, it will then switch to Slow mode. When both the input and output servo loops have switched
to Slow mode, the RDY output (pin 15) is forced low, indicating that the SRC has completed the rate estimation
process.
Copyright © 2006–2007, Texas Instruments Incorporated
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