Texas Instruments Three Phase BLDC Motor Kit with DRV8312 and InstaSPIN-Enabled Piccolo TMS320F28069M MCU DRV8312-69M-KI DRV8312-69M-KIT Datenbogen

Produktcode

DRV8312-69M-KIT

DRV8312
DRV8332

SLES256D – MAY 2010 – REVISED JANUARY 2014

www.ti.com

Figure 6

illustrates cycle-by-cycle operation with high

Table 2. Programming-Resistor Values and OC

side OC event and

Figure 7

shows cycle-by-cycle

Threshold (continued)

operation with low side OC. Dashed lines are the

OC-ADJUST RESISTOR

MAXIMUM CURRENT BEFORE

operation waveforms when no CBC event is triggered

VALUES (k

Ω)

OC OCCURS (A)

and solide lines show the waveforms when CBC

5.8

event is triggered. In CBC current limiting mode,

4.9

when low side FET OC is detected, the device will

4.1

turn off the affected low side FET and keep the high
side FET at the same half bridge off until next PWM

3.4

cycle; when high side FET OC is detected, the device

100

2.8

will turn off the affected high side FET and turn on the

120

2.4

low side FET at the half bridge until next PWM cycle.

150

1.9

It is important to note that if the input to a half bridge

200

1.4

is held to a constant value when an over current
event occurs in CBC, then the associated half bridge

It should be noted that a properly functioning

will be in a HI-Z state upon the over current event

overcurrent detector assumes the presence of a

ending. Cycling IN_X will allow OUT_X to resume

proper inductor or power ferrite bead at the power-

normal operation.

stage output. Short-circuit protection is not ensured
with a direct short at the output pins of the power

In OC latching shut down mode, the CBC current limit

stage.

and error recovery circuits are disabled and an
overcurrent

condition

will

cause

the

device

Overtemperature Protection

shutdown. After shutdown, RESET_A, RESET_B,
and RESET_C must be asserted to restore normal

The DRV8312/32 have a two-level temperature-

operation after the overcurrent condition is removed.

protection system that asserts an active-low warning
signal (OTW) when the device junction temperature

For

added

flexibility,

the

threshold

exceeds 125°C (nominal) and, if the device junction

programmable

using

single

external

resistor

temperature exceeds 150°C (nominal), the device is

connected between the OC_ADJ pin and AGND pin.

put into thermal shutdown, resulting in all half-bridge

See

Table 2

for information on the correlation

outputs being set in the high-impedance (Hi-Z) state

between programming-resistor value and the OC

and FAULT being asserted low. OTSD is latched in

threshold.

this case and RESET_A, RESET_B, and RESET_C

The values in

Table 2

show typical OC thresholds for

must be asserted low to clear the latch.

a given resistor. Assuming a fixed resistance on the
OC_ADJ pin across multiple devices, a 20% device-

Undervoltage Protection (UVP) and Power-On
Reset (POR)

to-device variation in OC threshold measurements is
possible. Therefore, this feature is designed for

The UVP and POR circuits of the DRV8312/32 fully

system protection and not for precise current control.

protect the device in any power-up / down and
brownout situation. While powering up, the POR

Table 2. Programming-Resistor Values and OC

circuit resets the overcurrent circuit and ensures that

Threshold

all circuits are fully operational when the GVDD_X

OC-ADJUST RESISTOR

MAXIMUM CURRENT BEFORE

and VDD supply voltages reach 9.8 V (typical).

VALUES (k

Ω)

OC OCCURS (A)

Although GVDD_X and VDD are independently

(1)

13.2

monitored, a supply voltage drop below the UVP
threshold on any VDD or GVDD_X pin results in all

11.6

half-bridge outputs immediately being set in the high-

10.7

impedance (Hi-Z) state and FAULT being asserted

9.7

low. The device automatically resumes operation

8.8

when all supply voltage on the bootstrap capacitors

7.4

have increased above the UVP threshold.

6.9

6.3

(1)

Recommended to use in OC Latching Mode Only

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