Texas Instruments DAC5681ZEVM - DAC5681Z Evaluation Module DAC5681ZEVM DAC5681ZEVM Datenbogen
Produktcode
DAC5681ZEVM
4.2
Input/Output Connectors
4.3
USB Interface
4.4
Power Management
4.5
Input Connector
DAC5681/81Z/82z EVM Hardware Description
www.ti.com
lists the input and output connectors on the EVM.
Table 2. Input and Output Connectors
Reference
Label
Connector Type
Description
Designator
DACB transformer output. Optional IOUTB2 output. Not populated
J1
IOUTB2
SMA
on DAC5681/81z.
J2
IOUTB1
SMA
Optional IOUTB1 output. Not populated on DAC5681/81z.
J3
IOUTA2
SMA
DACA transformer output. Optional IOUTA2 output.
J4
IOUTA1
SMA
Optional IOUTA1 output.
J5
SEMTEK
Input LVDS data to DAC. Output clock to data source.
J6
EXT_VCXO_P
SMA
External main clock input.
J7
EXT_VCXO_N
SMA
External VCXO negative connection. Not required.
J8
Y2A_CLK
SMA
Optional CDCM7005 clock output.
J9
EXT_REF_CLK
SMA
External reference clock input.
J10
Y2B_CLK
SMA
Optional CDCM7005 clock output.
J13
USB_CONN
USB
USB connector for software communication.
J14/J15
+1.8V_IN
Banana Plug
+1.8V connection pair.
J16
RFOUT
SMA
RF output from TRF3703.
J17/J18
+3.3V_IN
Banana Plug
+3.3V connection pair.
J19/J20
+5VA_IN
Banana Plug
+5V connection pair. Required only for RF measurements.
J23
RF_LO_IN
SMA
TRF3703 LO source input. Not populated on DAC5681/81z.
The DAC5681/81z/82z EVM has a 4-pin USB port connector that interfaces to a USB 1.1 (or later)
compliant USB port. Programming of the CDCM7005 and DAC is accomplished through this port.
compliant USB port. Programming of the CDCM7005 and DAC is accomplished through this port.
The DAC5681/81z/82z EVM requires 1.8-V and 3.3-V supplies for normal operation. An additional 5-V
supply is required supply power up the TRF3073 for RF measurements.
supply is required supply power up the TRF3073 for RF measurements.
The DAC5681/81z/82z EVM accepts LVDS inputs through a SEMTEK connector. These inputs drive
DCLK, SYNC and D15-D0 LVDS pairs on the DAC device. An LVDS clock signal from the CDCM7005 is
also output through this connector. This output clock is useful for synchronization with the pattern
generation source.
DCLK, SYNC and D15-D0 LVDS pairs on the DAC device. An LVDS clock signal from the CDCM7005 is
also output through this connector. This output clock is useful for synchronization with the pattern
generation source.
Table 3. Input Connector
Pin
Description
Pin
Description
47
D15P
101
D7P
49
D15N
103
D7N
53
D14P
107
D6P
55
D14N
109
D6N
59
D13P
113
D5P
61
D13N
115
D5N
65
D12P
119
D4P
8
DAC5681/81z/82z EVM
SLAU236A – November 2007 – Revised October 2008