Texas Instruments XIO2213B Evaluation Module / Reference Design XIO2213BEVM XIO2213BEVM Datenbogen
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XIO2213BEVM
SCPS210F – OCTOBER 2008 – REVISED MAY 2013
7.22 Link Enhancement Control Register
The link enhancement control register implements TI proprietary bits that are initialized by software or by a
serial EEPROM, if present. After these bits are set to 1b, their functionality is enabled only if bit 22
(aPhyEnhanceEnable) in the host controller control register at OHCI offset 50h/54h (see
serial EEPROM, if present. After these bits are set to 1b, their functionality is enabled only if bit 22
(aPhyEnhanceEnable) in the host controller control register at OHCI offset 50h/54h (see
Host Controller Control Register) is set to 1. See
for a complete description of the register
contents.
PCI register offset:
F4h
Register type:
Read/Write, Read only
Default value:
0000 4000h
BIT NUMBER
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESET STATE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
128
1394 OHCI PCI Configuration Space
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