Texas Instruments XIO2213B Evaluation Module / Reference Design XIO2213BEVM XIO2213BEVM Datenbogen
Produktcode
XIO2213BEVM
SCPS210F – OCTOBER 2008 – REVISED MAY 2013
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Overview
The Texas Instruments XIO2213B is a single-function PCI Express™ (PCIe) to PCI local bus translation
bridge, where the PCI bus interface is internally connected to a 1394b open host controller/link-layer
controller with a 3-port 1394b physical layer (PHY). When the XIO2213B is properly configured, this
solution provides full PCIe and 1394b functionality and performance.
bridge, where the PCI bus interface is internally connected to a 1394b open host controller/link-layer
controller with a 3-port 1394b physical layer (PHY). When the XIO2213B is properly configured, this
solution provides full PCIe and 1394b functionality and performance.
The TI XIO2213B is a PCIe to PCI translation bridge, where the PCI bus interface is internally connected
to a 1394b open host controller/link-layer controller with a 3-port 1394b PHY. The PCIe to PCI translation
bridge is fully compatible with the PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0. Also, the
bridge supports the standard PCI-to-PCI bridge programming model. The 1394b OHCI controller function
is fully compatible with IEEE Std 1394b and the latest 1394 Open Host Controller Interface (OHCI)
Specification.
to a 1394b open host controller/link-layer controller with a 3-port 1394b PHY. The PCIe to PCI translation
bridge is fully compatible with the PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0. Also, the
bridge supports the standard PCI-to-PCI bridge programming model. The 1394b OHCI controller function
is fully compatible with IEEE Std 1394b and the latest 1394 Open Host Controller Interface (OHCI)
Specification.
The XIO2213B simultaneously supports up to four posted write transactions, four nonposted transactions,
and four completion transactions pending in each direction at any time. Each posted write data queue and
completion data queue can store up to 8K bytes of data. The nonposted data queues can store up to 128
bytes of data.
and four completion transactions pending in each direction at any time. Each posted write data queue and
completion data queue can store up to 8K bytes of data. The nonposted data queues can store up to 128
bytes of data.
The PCIe interface supports a ×1 link operating at full 250 Mbit/s packet throughput in each direction
simultaneously. Also, the bridge supports the advanced error reporting capability including ECRC as
defined in the PCI Express Base Specification, Revision 1.1. Supplemental firmware or software is
required to fully utilize both of these features.
simultaneously. Also, the bridge supports the advanced error reporting capability including ECRC as
defined in the PCI Express Base Specification, Revision 1.1. Supplemental firmware or software is
required to fully utilize both of these features.
Robust pipeline architecture is implemented to minimize system latency. If parity errors are detected,
packet poisoning is supported for both upstream and downstream operations.
packet poisoning is supported for both upstream and downstream operations.
PCIe power management (PM) features include active-state link PM, PME mechanisms, and all
conventional PCI D states. If the active-state link PM is enabled, the link automatically saves power when
idle using the L0s and L1 states. PM active-state NAK, PM PME, and PME-to-ACK messages are
supported. The bridge is compliant with the latest PCI Bus Power Management Specification and provides
several low-power modes, which enable the host power system to further reduce power consumption
conventional PCI D states. If the active-state link PM is enabled, the link automatically saves power when
idle using the L0s and L1 states. PM active-state NAK, PM PME, and PME-to-ACK messages are
supported. The bridge is compliant with the latest PCI Bus Power Management Specification and provides
several low-power modes, which enable the host power system to further reduce power consumption
Eight general-purpose inputs and outputs (GPIOs), configured through accesses to the PCIe configuration
space, allow for further system control and customization.
space, allow for further system control and customization.
Deep FIFOs are provided to buffer 1394 data and accommodate large host bus latencies. The device
provides physical write posting and a highly tuned physical data path for SBP-2 performance. The device
is capable of transferring data between the PCIe bus and the 1394 bus at 100M bit/s, 200M bit/s, 400M
bit/s, and 800M bit/s. The device provides three 1394 ports that have separate cable bias (TPBIAS).
provides physical write posting and a highly tuned physical data path for SBP-2 performance. The device
is capable of transferring data between the PCIe bus and the 1394 bus at 100M bit/s, 200M bit/s, 400M
bit/s, and 800M bit/s. The device provides three 1394 ports that have separate cable bias (TPBIAS).
As required by the 1394 Open Host Controller Interface (OHCI) Specification, internal control registers are
memory mapped and nonprefetchable. This configuration header is accessed through configuration cycles
specified by PCIe, and it provides plug-and-play (PnP) compatibility.
memory mapped and nonprefetchable. This configuration header is accessed through configuration cycles
specified by PCIe, and it provides plug-and-play (PnP) compatibility.
The PHY provides the digital and analog transceiver functions needed to implement a 3-port node in a
cable-based 1394 network. Each cable port incorporates two differential line transceivers. The
transceivers include circuitry to monitor the line conditions as needed for determining connection status,
for initialization and arbitration, and for packet reception and transmission. An optional external 2-wire
serial EEPROM interface is provided to load the global unique ID for the 1394 fabric.
cable-based 1394 network. Each cable port incorporates two differential line transceivers. The
transceivers include circuitry to monitor the line conditions as needed for determining connection status,
for initialization and arbitration, and for packet reception and transmission. An optional external 2-wire
serial EEPROM interface is provided to load the global unique ID for the 1394 fabric.
The XIO2213B requires an external 98.304-MHz crystal oscillator to generate a reference clock. The
external clock drives an internal phase-locked loop (PLL), which generates the required reference signal.
This reference signal provides the clock signals that control transmission of the outbound encoded
information. The power-down (PD) function, when enabled by asserting the PD terminal high, stops
operation of the PLL. Data bits to be transmitted through the cable ports are latched internally, combined
serially, encoded, and transmitted at 98.304, 196.608, 393.216, 491.52, or 983.04 Mbit/s (referred to as
S100, S200, S400, S400B, or S800 speed, respectively) as the outbound information stream.
external clock drives an internal phase-locked loop (PLL), which generates the required reference signal.
This reference signal provides the clock signals that control transmission of the outbound encoded
information. The power-down (PD) function, when enabled by asserting the PD terminal high, stops
operation of the PLL. Data bits to be transmitted through the cable ports are latched internally, combined
serially, encoded, and transmitted at 98.304, 196.608, 393.216, 491.52, or 983.04 Mbit/s (referred to as
S100, S200, S400, S400B, or S800 speed, respectively) as the outbound information stream.
Copyright © 2008–2013, Texas Instruments Incorporated
Overview
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