Texas Instruments XIO2213B Evaluation Module / Reference Design XIO2213BEVM XIO2213BEVM Datenbogen
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XIO2213BEVM
SCPS210F – OCTOBER 2008 – REVISED MAY 2013
8.14 Posted Write Address High Register
The posted write address high register communicates error information if a write request is posted and an
error occurs while writing the posted data packet. See
error occurs while writing the posted data packet. See
for a complete description of the register
contents.
OHCI register offset:
3Ch
Register type:
Read/Update
Default value:
XXXX XXXXh
BIT NUMBER
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESET STATE
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Table 8-10. Posted Write Address High Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31-16
sourceID
RU
Source identification. This field is the 10-bit bus number (bits 31-22) and 6-bit node number
(bits 21-16) of the node that issued the write request that failed.
(bits 21-16) of the node that issued the write request that failed.
15-0
offsetHi
RU
Offset high. The upper 16 bits of the 1394 destination offset of the write request that failed.
8.15 Vendor ID Register
The vendor ID register holds the company ID of an organization that specifies any vendor-unique
registers. The controller implements TI unique behavior with regards to OHCI. Thus, this register is read
only and returns 0x08 0028h when read.
registers. The controller implements TI unique behavior with regards to OHCI. Thus, this register is read
only and returns 0x08 0028h when read.
OHCI register offset:
40h
Register type:
Read only
Default value:
0x08 0028h
BIT NUMBER
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESET STATE
0
0
0
0
0
x
x
1
0
0
0
0
1
0
0
0
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
8.16 Host Controller Control Register
The host controller control set/clear register pair provides flags for controlling the controller. See
for a complete description of the register contents.
OHCI register offset:
50h set register
54h clear register
54h clear register
Register type:
Read/Set/Clear/Update, Read/Set/Clear, Read/Clear, Read only
Default value:
0080 0000h
BIT NUMBER
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESET STATE
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
142
1394 OHCI Memory-Mapped Register Space
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