Texas Instruments XIO2213B Evaluation Module / Reference Design XIO2213BEVM XIO2213BEVM Datenbogen
Produktcode
XIO2213BEVM
SCPS210F – OCTOBER 2008 – REVISED MAY 2013
Table 8-11. Host Controller Control Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31
BIBimageValid
RSU
When bit 31 is set to 1b, the physical response unit is enabled to respond to block read requests
to host configuration ROM and to the mechanism for atomically updating configuration ROM.
Software creates a valid image of the bus_info_block in host configuration ROM before setting this
bit.
to host configuration ROM and to the mechanism for atomically updating configuration ROM.
Software creates a valid image of the bus_info_block in host configuration ROM before setting this
bit.
When this bit is cleared, the controller returns ack_type_error on block read requests to host
configuration ROM. Also, when this bit is cleared and a 1394 bus reset occurs, the configuration
ROM mapping register at OHCI offset 34h (see
configuration ROM. Also, when this bit is cleared and a 1394 bus reset occurs, the configuration
ROM mapping register at OHCI offset 34h (see
), configuration ROM header register
at OHCI offset 18h (see
), and bus options register at OHCI offset 20h (see
) are not updated.
Software can set this bit only when bit 17 (linkEnable) is 0b. Once bit 31 is set to 1b, it can be
cleared by a system (hardware) reset, a software reset, or if a fetch error occurs when the
controller loads bus_info_block registers from host memory.
cleared by a system (hardware) reset, a software reset, or if a fetch error occurs when the
controller loads bus_info_block registers from host memory.
30
noByteSwapData
RSC
Bit 30 controls whether physical accesses to locations outside the controller itself, as well as any
other DMA data accesses are byte swapped.
other DMA data accesses are byte swapped.
29
ack_Tardy_enable
RSC
Bit 29 controls the acknowledgement of ack_tardy. When bit 29 is set to 1b, ack_tardy may be
returned as an acknowledgment to accesses from the 1394 bus to the controller, including
accesses to the bus_info_block. The controller returns ack_tardy to all other asynchronous
packets addressed to the node. When the controller sends ack_tardy, bit 27 (ack_tardy) in the
interrupt event register at OHCI offset 80h/84h (see
returned as an acknowledgment to accesses from the 1394 bus to the controller, including
accesses to the bus_info_block. The controller returns ack_tardy to all other asynchronous
packets addressed to the node. When the controller sends ack_tardy, bit 27 (ack_tardy) in the
interrupt event register at OHCI offset 80h/84h (see
) is set to 1b to indicate the
attempted asynchronous access.
Software ensures that bit 27 (ack_tardy) in the interrupt event register is 0b. Software also
unmasks wake-up interrupt events such as bit 19 (phy) and bit 27 (ack_tardy) in the interrupt
event register before placing the controller into the D1 power mode.
unmasks wake-up interrupt events such as bit 19 (phy) and bit 27 (ack_tardy) in the interrupt
event register before placing the controller into the D1 power mode.
Software must not set this bit if the node is the 1394 bus manager.
28-24
RSVD
R
Reserved. Bits 28-24 return 00000b when read.
23
(1)
programPhyEnable
RC
Bit 23 informs upper-level software that lower-level software has consistently configured the IEEE
Std 1394a-2000 enhancements in the link and PHYs. When this bit is 1b, generic software such
as the OHCI driver is responsible for configuring IEEE Std 1394a-2000 enhancements in the PHY
and bit 22 (aPhyEnhanceEnable). When this bit is 0b, the generic software may not modify the
IEEE Std 1394a-2000 enhancements in the PHY and cannot interpret the setting of bit 22
(aPhyEnhanceEnable). This bit is initialized from serial EEPROM.
Std 1394a-2000 enhancements in the link and PHYs. When this bit is 1b, generic software such
as the OHCI driver is responsible for configuring IEEE Std 1394a-2000 enhancements in the PHY
and bit 22 (aPhyEnhanceEnable). When this bit is 0b, the generic software may not modify the
IEEE Std 1394a-2000 enhancements in the PHY and cannot interpret the setting of bit 22
(aPhyEnhanceEnable). This bit is initialized from serial EEPROM.
22
aPhyEnhanceEnabl
RSC
When bits 23 (programPhyEnable) and 17 (linkEnable) are 11b, the OHCI driver can set bit 22 to
e
1b to use all IEEE Std 1394a-2000 enhancements. When bit 23 (programPhyEnable) is cleared to
0b, the software does not change PHY enhancements or this bit.
0b, the software does not change PHY enhancements or this bit.
21-20
RSVD
R
Reserved. Bits 21 and 20 return 00b when read.
19
LPS
RSC
Bit 19 controls the link power status. Software must set this bit to 1b to permit the link-PHY
communication. A 0b prevents link-PHY communication.
communication. A 0b prevents link-PHY communication.
The OHCI link is divided into two clock domains (PCLK and PHY_SCLK). If software tries to
access any register in the PHY_SCLK domain while the PHY_SCLK is disabled, a target abort is
issued by the link. This problem can be avoided by setting bit 4 (DIS_TGT_ABT) to 1b in the PCI
miscellaneous configuration register at offset F0h in the PCI configuration space (see
access any register in the PHY_SCLK domain while the PHY_SCLK is disabled, a target abort is
issued by the link. This problem can be avoided by setting bit 4 (DIS_TGT_ABT) to 1b in the PCI
miscellaneous configuration register at offset F0h in the PCI configuration space (see
). This allows the link to respond to these types of request by returning all Fs (hex).
OHCI registers at offsets DCh-F0h and 100h-11Ch are in the PHY_SCLK domain.
After setting LPS, software must wait approximately 10 ms before attempting to access any of the
OHCI registers. This gives the PHY_SCLK time to stabilize.
OHCI registers. This gives the PHY_SCLK time to stabilize.
18
postedWriteEnable
RSC
Bit 18 enables (1) or disables (0) posted writes. Software changes this bit only when bit 17
(linkEnable) is 0b.
(linkEnable) is 0b.
17
linkEnable
RSC
Bit 17 is cleared to 0b by either a system (hardware) or software reset. Software must set this bit
to 1b when the system is ready to begin operation and then force a bus reset. This bit is
necessary to keep other nodes from sending transactions before the local system is ready. When
this bit is cleared, the controller is logically and immediately disconnected from the 1394 bus, no
packets are received or processed, nor are packets transmitted.
to 1b when the system is ready to begin operation and then force a bus reset. This bit is
necessary to keep other nodes from sending transactions before the local system is ready. When
this bit is cleared, the controller is logically and immediately disconnected from the 1394 bus, no
packets are received or processed, nor are packets transmitted.
16
SoftReset
RSCU
When bit 16 is set to 1b, all states are reset, all FIFOs are flushed, and all OHCI registers are set
to their system (hardware) reset values, unless otherwise specified. PCI registers are not affected
by this bit. This bit remains set to 1b while the software reset is in progress and reverts back to 0b
when the reset has completed.
to their system (hardware) reset values, unless otherwise specified. PCI registers are not affected
by this bit. This bit remains set to 1b while the software reset is in progress and reverts back to 0b
when the reset has completed.
15-0
RSVD
R
Reserved. Bits 15-0 return 0000h when read.
(1)
This bit is reset by PERST or FRST.
144
1394 OHCI Memory-Mapped Register Space
Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: