Texas Instruments XIO2213B Evaluation Module / Reference Design XIO2213BEVM XIO2213BEVM Datenbogen
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XIO2213BEVM
SCPS210F – OCTOBER 2008 – REVISED MAY 2013
9
1394 OHCI Memory-Mapped TI Extension Register Space
The TI extension base address register provides a method of accessing memory-mapped TI extension
registers. See
registers. See
, TI Extension Base Address Register, for register bit field details. See
for the TI extension register listing.
Table 9-1. TI Extension Register Map
REGISTER NAME
OFFSET
Reserved
00h-A7Fh
Isochronous receive digital video enhancement set
A80h
Isochronous receive digital video enhancement clear
A84h
Link enhancement control set
A88h
Link enhancement control clear
A8Ch
Isochronous transmit context 0 timestamp offset
A90h
Isochronous transmit context 1 timestamp offset
A94h
Isochronous transmit context 2 timestamp offset
A98h
Isochronous transmit context 3 timestamp offset
A9Ch
Isochronous transmit context 4 timestamp offset
AA0h
Isochronous transmit context 5 timestamp offset
AA4h
Isochronous transmit context 6 timestamp offset
AA8h
Isochronous transmit context 7 timestamp offset
AACh
Reserved
AB0h-FFFh
9.1
Digital Video (DV) and MPEG2 Timestamp Enhancements
The DV timestamp enhancements are enabled by bit 8 (enab_dv_ts) in the link enhancement control
register located at PCI offset F4h, and are aliased in TI extension register space at offset A88h (set) and
A8Ch (clear).
register located at PCI offset F4h, and are aliased in TI extension register space at offset A88h (set) and
A8Ch (clear).
The DV and MPEG transmit enhancements are enabled separately by bits in the link enhancement control
register located in PCI configuration space at PCI offset F4h. The link enhancement control register is also
aliased as a set/clear register in TI extension space at offset A88h (set) and A8Ch (clear).
register located in PCI configuration space at PCI offset F4h. The link enhancement control register is also
aliased as a set/clear register in TI extension space at offset A88h (set) and A8Ch (clear).
Bit 8 (enab_dv_ts) of the link enhancement control register enables DV timestamp support. When
enabled, the link calculates a timestamp based on the cycle timer and the timestamp offset register and
substitutes it in the SYT field of the CIP once per DV frame.
enabled, the link calculates a timestamp based on the cycle timer and the timestamp offset register and
substitutes it in the SYT field of the CIP once per DV frame.
Bit 10 (enab_mpeg_ts) of the link enhancement control register enables MPEG timestamp support. Two
MPEG timestamp modes are supported. The default mode calculates an initial delta that is added to the
calculated timestamp in addition to a user-defined offset. The initial offset is calculated as the difference in
the intended transmit cycle count and the cycle count field of the timestamp in the first TSP of the MPEG2
stream. The use of the initial delta can be controlled by bit 31 (DisableInitialOffset) in the timestamp offset
register (see
MPEG timestamp modes are supported. The default mode calculates an initial delta that is added to the
calculated timestamp in addition to a user-defined offset. The initial offset is calculated as the difference in
the intended transmit cycle count and the cycle count field of the timestamp in the first TSP of the MPEG2
stream. The use of the initial delta can be controlled by bit 31 (DisableInitialOffset) in the timestamp offset
register (see
The MPEG2 timestamp enhancements are enabled by bit 10 (enab_mpeg_ts) in the link enhancement
control register located at PCI offset F4h, and aliased in TI extension register space at offset A88h (set)
and A8Ch (clear).
control register located at PCI offset F4h, and aliased in TI extension register space at offset A88h (set)
and A8Ch (clear).
When bit 10 (enab_mpeg_ts) is set to 1b, the hardware applies the timestamp enhancements to
isochronous transmit packets that have the tag field equal to 01b in the isochronous packet header and a
FMT field equal to 10h.
isochronous transmit packets that have the tag field equal to 01b in the isochronous packet header and a
FMT field equal to 10h.
174
1394 OHCI Memory-Mapped TI Extension Register Space
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