Texas Instruments XIO2213B Evaluation Module / Reference Design XIO2213BEVM XIO2213BEVM Datenbogen
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XIO2213BEVM
SCPS210F – OCTOBER 2008 – REVISED MAY 2013
Table 9-2. Isochronous Receive Digital Video Enhancement Registers Description (continued)
BIT
FIELD NAME
TYPE
DESCRIPTION
4
CIP_Strip1
RSC
When bit 4 is set to 1b, the isochronous receive context 1 strips the first two quadlets of payload. This
bit is only interpreted when bit 30 (isochHeader) in the isochronous receive context control register at
OHCI offset 420h/424h (see
bit is only interpreted when bit 30 (isochHeader) in the isochronous receive context control register at
OHCI offset 420h/424h (see
) is cleared to 0b.
3-2
RSVD
R
Reserved. Bits 3 and 2 return 00b when read.
1
DV_Branch0
RSC
When bit 1 is set to 1b, the isochronous receive context 0 synchronizes reception to the DV frame
start tag in bufferfill mode if input_more.b = 01b and jumps to the descriptor pointed to by frameBranch
a DV frame start tag is received out of place. This bit is only interpreted when bit 0 (CIP_Strip0) is set
to 1b and bit 30 (isochHeader) in the isochronous receive context control register at OHCI offset
400h/404h (see
start tag in bufferfill mode if input_more.b = 01b and jumps to the descriptor pointed to by frameBranch
a DV frame start tag is received out of place. This bit is only interpreted when bit 0 (CIP_Strip0) is set
to 1b and bit 30 (isochHeader) in the isochronous receive context control register at OHCI offset
400h/404h (see
) is cleared to 0b.
0
CIP_Strip0
RSC
When bit 0 is set to 1b, the isochronous receive context 0 strips the first two quadlets of payload. This
bit is only interpreted when bit 30 (isochHeader) in the isochronous receive context control register at
OHCI offset 400h/404h (see
bit is only interpreted when bit 30 (isochHeader) in the isochronous receive context control register at
OHCI offset 400h/404h (see
) is cleared to 0b.
9.4
Link Enhancement Control Registers
These registers are a memory-mapped set/clear registers that are an alias of the link enhancement control
register at PCI offset F4h. These bits may be initialized by software. Some of the bits may also be
initialized by a serial EEPROM, if one is present, as noted in the following bit descriptions. If the bits are to
be initialized by software, the bits must be initialized prior to setting bit 19 (LPS) in the host controller
control register at OHCI offset 50h/54h (see
register at PCI offset F4h. These bits may be initialized by software. Some of the bits may also be
initialized by a serial EEPROM, if one is present, as noted in the following bit descriptions. If the bits are to
be initialized by software, the bits must be initialized prior to setting bit 19 (LPS) in the host controller
control register at OHCI offset 50h/54h (see
). See
for a complete description of
the register contents.
TI extension register offset:
A88h set register
A8Ch clear register
A8Ch clear register
Register type:
Read/Set/Clear, Read only
Default value:
0000 0000h
BIT NUMBER
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESET STATE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
Table 9-3. Link Enhancement Control Registers Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31-16
RSVD
R
Reserved. Bits 31-16 return 0000h when read.
15
(1)
dis_at_pipleline
RW
Disable AT pipelining. When bit 15 is set to 1b, out-of-order AT pipelining is disabled. The default
value for this bit is 0b.
value for this bit is 0b.
14
(1)
RSVD
RW
Reserved. Bit 14 defaults to 0b and must remain 0b for normal operation of the OHCI core.
(1)
This bit is reset by PERST or FRST.
176
1394 OHCI Memory-Mapped TI Extension Register Space
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