Texas Instruments XIO2213B Evaluation Module / Reference Design XIO2213BEVM XIO2213BEVM Datenbogen
Produktcode
XIO2213BEVM
VDD_15 and
VDDA_15
VDD_33 and
VDDA_33
REFCLK
PERST
100 ms
100 ms
SCPS210F – OCTOBER 2008 – REVISED MAY 2013
3.1.1
Power-Up Sequence
1. Assert PERST to the device.
2. Apply 1.5-V and 3.3-V voltages.
3. Apply a stable PCIe reference clock.
4. To meet PCIe specification requirements, PERST cannot be deasserted until the following two delay
requirements are satisfied:
–
Wait a minimum of 100 s after applying a stable PCIe reference clock. The 100-s limit satisfies the
requirement for stable device clocks by the deassertion of PERST.
requirement for stable device clocks by the deassertion of PERST.
–
Wait a minimum of 100 ms after applying power. The 100-ms limit satisfies the requirement for
stable power by the deassertion of PERST.
stable power by the deassertion of PERST.
See the power-up sequencing diagram in
Figure 3-2. Power-Up Sequence
32
Feature/Protocol Descriptions
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